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authorNilay Vaish <nilay@cs.wisc.edu>2011-08-29 05:10:23 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2011-08-29 05:10:23 -0500
commit1bbca50491202c6527743fcca9030d55b4ddc06b (patch)
tree8fb0e71ae58833d3a9b528ab2d6769245f09901a /src/mem/ruby/system
parenta08cc94936d4960f837731537b454a63657efd04 (diff)
downloadgem5-1bbca50491202c6527743fcca9030d55b4ddc06b.tar.xz
Ruby: Remove some unused code
Diffstat (limited to 'src/mem/ruby/system')
-rw-r--r--src/mem/ruby/system/CacheMemory.hh1
-rw-r--r--src/mem/ruby/system/Sequencer.cc18
-rw-r--r--src/mem/ruby/system/Sequencer.hh3
3 files changed, 0 insertions, 22 deletions
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index c355ae2e3..f0acba9cb 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -36,7 +36,6 @@
#include "base/hashmap.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/protocol/GenericRequestType.hh"
-#include "mem/protocol/MachineType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index ceed068e8..711ef12ed 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -504,11 +504,6 @@ Sequencer::hitCallback(SequencerRequest* srequest,
success ? "Done" : "SC_Failed", "", "",
ruby_request.m_PhysicalAddress, miss_latency);
}
-#if 0
- if (request.getPrefetch() == PrefetchBit_Yes) {
- return; // Ignore the prefetch
- }
-#endif
// update the data
if (ruby_request.data != NULL) {
@@ -702,19 +697,6 @@ Sequencer::issueRequest(const RubyRequest& request)
m_mandatory_q_ptr->enqueue(msg, latency);
}
-#if 0
-bool
-Sequencer::tryCacheAccess(const Address& addr, RubyRequestType type,
- RubyAccessMode access_mode,
- int size, DataBlock*& data_ptr)
-{
- CacheMemory *cache =
- (type == RubyRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
-
- return cache->tryCacheAccess(line_address(addr), type, data_ptr);
-}
-#endif
-
template <class KEY, class VALUE>
std::ostream &
operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 885910251..0589d8bbc 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -112,9 +112,6 @@ class Sequencer : public RubyPort, public Consumer
void removeRequest(SequencerRequest* request);
private:
- bool tryCacheAccess(const Address& addr, RubyRequestType type,
- const Address& pc, RubyAccessMode access_mode,
- int size, DataBlock*& data_ptr);
void issueRequest(const RubyRequest& request);
void hitCallback(SequencerRequest* request,