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| author | Derek Hower <drh5@cs.wisc.edu> | 2009-08-03 11:39:08 -0500 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2009-08-03 11:39:08 -0500 |
| commit | ac15e42c1782f39882ab47745ed690b7d30b1f86 (patch) | |
| tree | 20f05d39bdf701cdd2ca0b020388687d7526a42c /src/mem/ruby/system | |
| parent | 38c2af17a557e5b7420a2ad15b13316acbde588d (diff) | |
| parent | 8623b4b6ea12a576634431632d02bcba200ca704 (diff) | |
| download | gem5-ac15e42c1782f39882ab47745ed690b7d30b1f86.tar.xz | |
Automated merge with ssh://hg@m5sim.org/m5
Diffstat (limited to 'src/mem/ruby/system')
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.hh | 6 | ||||
| -rw-r--r-- | src/mem/ruby/system/DMASequencer.cc | 1 | ||||
| -rw-r--r-- | src/mem/ruby/system/System.cc | 15 | ||||
| -rw-r--r-- | src/mem/ruby/system/TBETable.hh | 1 |
4 files changed, 15 insertions, 8 deletions
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index cfaa229a5..7a46bd3a5 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -127,6 +127,7 @@ public: void print(ostream& out) const; void printData(ostream& out) const; + void clearStats() const; void printStats(ostream& out) const; private: @@ -561,6 +562,11 @@ void CacheMemory::printData(ostream& out) const out << "printData() not supported" << endl; } +inline void CacheMemory::clearStats() const +{ + m_profiler_ptr->clearStats(); +} + inline void CacheMemory::printStats(ostream& out) const { diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index 58ec7bb45..d29dba602 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -51,6 +51,7 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request) case RubyRequestType_Locked_Write: case RubyRequestType_RMW_Read: case RubyRequestType_RMW_Write: + case RubyRequestType_NUM: assert(0); } diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc index 2c24c9ade..ad67cdc80 100644 --- a/src/mem/ruby/system/System.cc +++ b/src/mem/ruby/system/System.cc @@ -347,15 +347,16 @@ void RubySystem::printStats(ostream& out) void RubySystem::clearStats() const { - /* m_profiler_ptr->clearStats(); - for (int i=0; i<m_rubyRequestQueues.size(); i++) - for (int j=0;j<m_rubyRequestQueues[i].size(); j++) - m_rubyRequestQueues[i][j]->clearStats(); m_network_ptr->clearStats(); - for (int i=0; i < MachineType_base_level(MachineType_NUM); i++) - m_controllers[i][0]->clearStats(); - */ + for (map<string, CacheMemory*>::const_iterator it = m_caches.begin(); + it != m_caches.end(); it++) { + (*it).second->clearStats(); + } + for (map<string, AbstractController*>::const_iterator it = m_controllers.begin(); + it != m_controllers.end(); it++) { + (*it).second->clearStats(); + } } void RubySystem::recordCacheContents(CacheRecorder& tr) const diff --git a/src/mem/ruby/system/TBETable.hh b/src/mem/ruby/system/TBETable.hh index 7d2daa55a..2b00f7a06 100644 --- a/src/mem/ruby/system/TBETable.hh +++ b/src/mem/ruby/system/TBETable.hh @@ -128,7 +128,6 @@ void TBETable<ENTRY>::allocate(const Address& address) { assert(isPresent(address) == false); assert(m_map.size() < m_number_of_TBEs); - g_system_ptr->getProfiler()->L2tbeUsageSample(m_map.size()); m_map.add(address, ENTRY()); } |