Ruby: Remove RubyEventQueue

This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.

12 files changed, 41 insertions, 66 deletions

diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index 6ba879e90..81d73f5b4 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -154,8 +154,7 @@ CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
     if (loc != -1) {
         // Do we even have a tag match?
         AbstractCacheEntry* entry = m_cache[cacheSet][loc];
-        m_replacementPolicy_ptr->
-            touch(cacheSet, loc, g_eventQueue_ptr->getTime());
+        m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
         data_ptr = &(entry->getDataBlk());
 
         if (entry->m_Permission == AccessPermission_Read_Write) {
@@ -183,8 +182,7 @@ CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
     if (loc != -1) {
         // Do we even have a tag match?
         AbstractCacheEntry* entry = m_cache[cacheSet][loc];
-        m_replacementPolicy_ptr->
-            touch(cacheSet, loc, g_eventQueue_ptr->getTime());
+        m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
         data_ptr = &(entry->getDataBlk());
 
         return m_cache[cacheSet][loc]->m_Permission !=
@@ -258,8 +256,7 @@ CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry)
             set[i]->m_locked = -1;
             m_tag_index[address] = i;
 
-            m_replacementPolicy_ptr->
-                touch(cacheSet, i, g_eventQueue_ptr->getTime());
+            m_replacementPolicy_ptr->touch(cacheSet, i, curTick());
 
             return entry;
         }
@@ -324,8 +321,7 @@ CacheMemory::setMRU(const Address& address)
     int loc = findTagInSet(cacheSet, address);
 
     if(loc != -1)
-        m_replacementPolicy_ptr->
-             touch(cacheSet, loc, g_eventQueue_ptr->getTime());
+        m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
 }
 
 void
@@ -540,4 +536,3 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr)
         return true;
     }
 }
-
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 8adc892a7..a4950a09b 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -29,7 +29,6 @@
 #ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
 #define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
 
-#include <iostream>
 #include <string>
 #include <vector>
 
@@ -172,4 +171,3 @@ class CacheMemory : public SimObject
 };
 
 #endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
-
diff --git a/src/mem/ruby/system/RubyMemoryControl.cc b/src/mem/ruby/system/RubyMemoryControl.cc
index 54585e275..230f652c2 100644
--- a/src/mem/ruby/system/RubyMemoryControl.cc
+++ b/src/mem/ruby/system/RubyMemoryControl.cc
@@ -279,7 +279,7 @@ RubyMemoryControl::~RubyMemoryControl()
 void
 RubyMemoryControl::enqueue(const MsgPtr& message, int latency)
 {
-    Time current_time = g_eventQueue_ptr->getTime();
+    Time current_time = g_system_ptr->getTime();
     Time arrival_time = current_time + latency;
     const MemoryMsg* memMess = safe_cast<const MemoryMsg*>(message.get());
     physical_address_t addr = memMess->getAddress().getAddress();
@@ -302,7 +302,7 @@ RubyMemoryControl::enqueueMemRef(MemoryNode& memRef)
     DPRINTF(RubyMemory,
             "New memory request%7d: %#08x %c arrived at %10d bank = %3x sched %c\n",
             m_msg_counter, addr, memRef.m_is_mem_read ? 'R':'W',
-            memRef.m_time * g_eventQueue_ptr->getClock(),
+            memRef.m_time * g_system_ptr->getClock(),
             bank, m_event.scheduled() ? 'Y':'N');
 
     m_profiler_ptr->profileMemReq(bank);
@@ -347,7 +347,7 @@ bool
 RubyMemoryControl::isReady()
 {
     return ((!m_response_queue.empty()) &&
-            (m_response_queue.front().m_time <= g_eventQueue_ptr->getTime()));
+            (m_response_queue.front().m_time <= g_system_ptr->getTime()));
 }
 
 void
@@ -377,17 +377,17 @@ RubyMemoryControl::printStats(ostream& out) const
 void
 RubyMemoryControl::enqueueToDirectory(MemoryNode req, int latency)
 {
-    Time arrival_time = g_eventQueue_ptr->getTime()
+    Time arrival_time = g_system_ptr->getTime()
         + (latency * m_mem_bus_cycle_multiplier);
     req.m_time = arrival_time;
     m_response_queue.push_back(req);
 
     DPRINTF(RubyMemory, "Enqueueing msg %#08x %c back to directory at %15d\n",
             req.m_addr, req.m_is_mem_read ? 'R':'W',
-            arrival_time * g_eventQueue_ptr->getClock());
+            arrival_time * g_system_ptr->getClock());
 
     // schedule the wake up
-    g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, arrival_time);
+    m_consumer_ptr->scheduleEventAbsolute(arrival_time);
 }
 
 // getBank returns an integer that is unique for each
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index c8580bb5c..b24f649a5 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -198,7 +198,7 @@ RubyPort::M5Port::recvTimingReq(PacketPtr pkt)
 
         // send next cycle
         ruby_port->pio_port.schedTimingReq(pkt, curTick() +
-                                           g_eventQueue_ptr->getClock());
+                                           g_system_ptr->getClock());
         return true;
     }
 
@@ -651,7 +651,7 @@ RubyPort::M5Port::hitCallback(PacketPtr pkt)
     if (needsResponse) {
         DPRINTF(RubyPort, "Sending packet back over port\n");
         // send next cycle
-        schedTimingResp(pkt, curTick() + g_eventQueue_ptr->getClock());
+        schedTimingResp(pkt, curTick() + g_system_ptr->getClock());
     } else {
         delete pkt;
     }
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index a4cdca53f..01d34814f 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -43,11 +43,9 @@
 #include "mem/ruby/common/Global.hh"
 #include "mem/ruby/profiler/Profiler.hh"
 #include "mem/ruby/slicc_interface/RubyRequest.hh"
-#include "mem/ruby/system/CacheMemory.hh"
 #include "mem/ruby/system/Sequencer.hh"
 #include "mem/ruby/system/System.hh"
 #include "mem/packet.hh"
-#include "params/RubySequencer.hh"
 
 using namespace std;
 
@@ -88,7 +86,7 @@ void
 Sequencer::wakeup()
 {
     // Check for deadlock of any of the requests
-    Time current_time = g_eventQueue_ptr->getTime();
+    Time current_time = g_system_ptr->getTime();
 
     // Check across all outstanding requests
     int total_outstanding = 0;
@@ -131,7 +129,7 @@ Sequencer::wakeup()
     if (m_outstanding_count > 0) {
         // If there are still outstanding requests, keep checking
         schedule(deadlockCheckEvent,
-                 m_deadlock_threshold * g_eventQueue_ptr->getClock() +
+                 m_deadlock_threshold * g_system_ptr->getClock() +
                  curTick());
     }
 }
@@ -156,7 +154,7 @@ Sequencer::printProgress(ostream& out) const
 #if 0
     int total_demand = 0;
     out << "Sequencer Stats Version " << m_version << endl;
-    out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
+    out << "Current time = " << g_system_ptr->getTime() << endl;
     out << "---------------" << endl;
     out << "outstanding requests" << endl;
 
@@ -212,7 +210,7 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
     // See if we should schedule a deadlock check
     if (deadlockCheckEvent.scheduled() == false) {
         schedule(deadlockCheckEvent,
-                 m_deadlock_threshold * g_eventQueue_ptr->getClock()
+                 m_deadlock_threshold * g_system_ptr->getClock()
                  + curTick());
     }
 
@@ -239,7 +237,7 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
         if (r.second) {
             RequestTable::iterator i = r.first;
             i->second = new SequencerRequest(pkt, request_type,
-                                             g_eventQueue_ptr->getTime());
+                                             g_system_ptr->getTime());
             m_outstanding_count++;
         } else {
           // There is an outstanding write request for the cache line
@@ -260,7 +258,7 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
         if (r.second) {
             RequestTable::iterator i = r.first;
             i->second = new SequencerRequest(pkt, request_type,
-                                             g_eventQueue_ptr->getTime());
+                                             g_system_ptr->getTime());
             m_outstanding_count++;
         } else {
             // There is an outstanding read request for the cache line
@@ -476,8 +474,8 @@ Sequencer::hitCallback(SequencerRequest* srequest,
         m_dataCache_ptr->setMRU(request_line_address);
     }
 
-    assert(g_eventQueue_ptr->getTime() >= issued_time);
-    Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
+    assert(g_system_ptr->getTime() >= issued_time);
+    Time miss_latency = g_system_ptr->getTime() - issued_time;
 
     // Profile the miss latency for all non-zero demand misses
     if (miss_latency != 0) {
@@ -488,7 +486,7 @@ Sequencer::hitCallback(SequencerRequest* srequest,
                                                    initialRequestTime,
                                                    forwardRequestTime,
                                                    firstResponseTime,
-                                                   g_eventQueue_ptr->getTime());
+                                                   g_system_ptr->getTime());
         }
 
         if (mach == GenericMachineType_Directory) {
@@ -496,7 +494,7 @@ Sequencer::hitCallback(SequencerRequest* srequest,
                                                    initialRequestTime,
                                                    forwardRequestTime,
                                                    firstResponseTime,
-                                                   g_eventQueue_ptr->getTime());
+                                                   g_system_ptr->getTime());
         }
 
         DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index a912347aa..dbdfca38e 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -36,13 +36,11 @@
 #include "mem/protocol/RubyRequestType.hh"
 #include "mem/protocol/SequencerRequestType.hh"
 #include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Consumer.hh"
+#include "mem/ruby/system/CacheMemory.hh"
 #include "mem/ruby/system/RubyPort.hh"
+#include "params/RubySequencer.hh"
 
 class DataBlock;
-class CacheMemory;
-
-struct RubySequencerParams;
 
 struct SequencerRequest
 {
@@ -57,7 +55,7 @@ struct SequencerRequest
 
 std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
 
-class Sequencer : public RubyPort, public Consumer
+class Sequencer : public RubyPort
 {
   public:
     typedef RubySequencerParams Params;
diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc
index b06e8b7ed..7921d306d 100644
--- a/src/mem/ruby/system/System.cc
+++ b/src/mem/ruby/system/System.cc
@@ -77,7 +77,6 @@ RubySystem::RubySystem(const Params *p)
         m_memory_size_bits = floorLog2(m_memory_size_bytes);
     }
 
-    g_eventQueue_ptr = new RubyEventQueue(p->eventq, m_clock);
     g_system_ptr = this;
     if (p->no_mem_vec) {
         m_mem_vec_ptr = NULL;
@@ -423,13 +422,13 @@ RubySystem::checkGlobalCoherenceInvariant(const Address& addr)
                 WARN_EXPR(exclusive);
                 WARN_EXPR(m_chip_vector[i]->getID());
                 WARN_EXPR(addr);
-                WARN_EXPR(g_eventQueue_ptr->getTime());
+                WARN_EXPR(getTime());
                 ERROR_MSG("Coherence Violation Detected -- 2 exclusive chips");
             } else if (sharedDetected) {
                 WARN_EXPR(lastShared);
                 WARN_EXPR(m_chip_vector[i]->getID());
                 WARN_EXPR(addr);
-                WARN_EXPR(g_eventQueue_ptr->getTime());
+                WARN_EXPR(getTime());
                 ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
             } else {
                 exclusive = m_chip_vector[i]->getID();
@@ -442,7 +441,7 @@ RubySystem::checkGlobalCoherenceInvariant(const Address& addr)
                 WARN_EXPR(lastShared);
                 WARN_EXPR(exclusive);
                 WARN_EXPR(addr);
-                WARN_EXPR(g_eventQueue_ptr->getTime());
+                WARN_EXPR(getTime());
                 ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
             }
         }
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index bbb14667f..e6501f7bf 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -37,7 +37,6 @@
 
 #include "base/callback.hh"
 #include "mem/ruby/common/Global.hh"
-#include "mem/ruby/eventqueue/RubyEventQueue.hh"
 #include "mem/ruby/recorder/CacheRecorder.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 #include "mem/ruby/system/MemoryVector.hh"
@@ -78,6 +77,8 @@ class RubySystem : public SimObject
     static int getBlockSizeBits() { return m_block_size_bits; }
     static uint64 getMemorySizeBytes() { return m_memory_size_bytes; }
     static int getMemorySizeBits() { return m_memory_size_bits; }
+    Tick getTime() const { return curTick() / m_clock; }
+    Tick getClock() const { return m_clock; }
 
     // Public Methods
     static Network*
@@ -87,12 +88,6 @@ class RubySystem : public SimObject
         return m_network_ptr;
     }
 
-    static RubyEventQueue*
-    getEventQueue()
-    {
-        return g_eventQueue_ptr;
-    }
-
     Profiler*
     getProfiler()
     {
@@ -111,11 +106,6 @@ class RubySystem : public SimObject
     void clearStats() const;
 
     uint64 getInstructionCount(int thread) { return 1; }
-    static uint64
-    getCycleCount(int thread)
-    {
-        return g_eventQueue_ptr->getTime();
-    }
 
     void print(std::ostream& out) const;
 
diff --git a/src/mem/ruby/system/TimerTable.cc b/src/mem/ruby/system/TimerTable.cc
index d5df8fe18..6702411a5 100644
--- a/src/mem/ruby/system/TimerTable.cc
+++ b/src/mem/ruby/system/TimerTable.cc
@@ -27,7 +27,7 @@
  */
 
 #include "mem/ruby/common/Global.hh"
-#include "mem/ruby/eventqueue/RubyEventQueue.hh"
+#include "mem/ruby/system/System.hh"
 #include "mem/ruby/system/TimerTable.hh"
 
 TimerTable::TimerTable()
@@ -48,7 +48,7 @@ TimerTable::isReady() const
         updateNext();
     }
     assert(m_next_valid);
-    return (g_eventQueue_ptr->getTime() >= m_next_time);
+    return (g_system_ptr->getTime() >= m_next_time);
 }
 
 const Address&
@@ -69,10 +69,10 @@ TimerTable::set(const Address& address, Time relative_latency)
     assert(address == line_address(address));
     assert(relative_latency > 0);
     assert(!m_map.count(address));
-    Time ready_time = g_eventQueue_ptr->getTime() + relative_latency;
+    Time ready_time = g_system_ptr->getTime() + relative_latency;
     m_map[address] = ready_time;
     assert(m_consumer_ptr != NULL);
-    g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, ready_time);
+    m_consumer_ptr->scheduleEventAbsolute(ready_time);
     m_next_valid = false;
 
     // Don't always recalculate the next ready address
diff --git a/src/mem/ruby/system/TimerTable.hh b/src/mem/ruby/system/TimerTable.hh
index e4419d4d3..4335b6605 100644
--- a/src/mem/ruby/system/TimerTable.hh
+++ b/src/mem/ruby/system/TimerTable.hh
@@ -31,12 +31,11 @@
 
 #include <cassert>
 #include <iostream>
+#include <map>
 #include <string>
 
 #include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
-
-class Consumer;
+#include "mem/ruby/common/Consumer.hh"
 
 class TimerTable
 {
diff --git a/src/mem/ruby/system/WireBuffer.cc b/src/mem/ruby/system/WireBuffer.cc
index f007d6c51..fb12998be 100644
--- a/src/mem/ruby/system/WireBuffer.cc
+++ b/src/mem/ruby/system/WireBuffer.cc
@@ -74,13 +74,13 @@ void
 WireBuffer::enqueue(MsgPtr message, int latency)
 {
     m_msg_counter++;
-    Time current_time = g_eventQueue_ptr->getTime();
+    Time current_time = g_system_ptr->getTime();
     Time arrival_time = current_time + latency;
     assert(arrival_time > current_time);
     MessageBufferNode thisNode(arrival_time, m_msg_counter, message);
     m_message_queue.push_back(thisNode);
     if (m_consumer_ptr != NULL) {
-        g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, arrival_time);
+        m_consumer_ptr->scheduleEventAbsolute(arrival_time);
     } else {
         panic("No Consumer for WireBuffer! %s\n", *this);
     }
@@ -123,19 +123,18 @@ WireBuffer::recycle()
     MessageBufferNode node = m_message_queue.front();
     pop_heap(m_message_queue.begin(), m_message_queue.end(),
         greater<MessageBufferNode>());
-    node.m_time = g_eventQueue_ptr->getTime() + 1;
+    node.m_time = g_system_ptr->getTime() + 1;
     m_message_queue.back() = node;
     push_heap(m_message_queue.begin(), m_message_queue.end(),
         greater<MessageBufferNode>());
-    g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr,
-        g_eventQueue_ptr->getTime() + 1);
+    m_consumer_ptr->scheduleEventAbsolute(g_system_ptr->getTime() + 1);
 }
 
 bool
 WireBuffer::isReady()
 {
     return ((!m_message_queue.empty()) &&
-            (m_message_queue.front().m_time <= g_eventQueue_ptr->getTime()));
+            (m_message_queue.front().m_time <= g_system_ptr->getTime()));
 }
 
 void
diff --git a/src/mem/ruby/system/WireBuffer.hh b/src/mem/ruby/system/WireBuffer.hh
index bc3afa2da..c22fab70b 100644
--- a/src/mem/ruby/system/WireBuffer.hh
+++ b/src/mem/ruby/system/WireBuffer.hh
@@ -38,7 +38,6 @@
 
 #include "mem/ruby/buffers/MessageBufferNode.hh"
 #include "mem/ruby/common/Global.hh"
-#include "mem/ruby/eventqueue/RubyEventQueue.hh"
 #include "params/RubyWireBuffer.hh"
 #include "sim/sim_object.hh"