diff options
| author | Gabe Black <gabeblack@google.com> | 2019-04-22 19:45:10 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-04-28 01:19:40 +0000 |
| commit | cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 (patch) | |
| tree | 893cea35432466600b55a2e4434ed61ba1e28f69 /src/mem/ruby/system | |
| parent | 3cfff8574a19536e2b3d057b43b59fcf35932c81 (diff) | |
| download | gem5-cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9.tar.xz | |
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/mem/ruby/system')
| -rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 4 | ||||
| -rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 4 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.py | 4 | ||||
| -rw-r--r-- | src/mem/ruby/system/WeightedLRUReplacementPolicy.py | 1 |
4 files changed, 6 insertions, 7 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 795b473c7..ff3bbe8f0 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -52,7 +52,7 @@ #include "sim/system.hh" RubyPort::RubyPort(const Params *p) - : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version), + : ClockedObject(p), m_ruby_system(p->ruby_system), m_version(p->version), m_controller(NULL), m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), system(p->system), pioMasterPort(csprintf("%s.pio-master-port", name()), this), @@ -117,7 +117,7 @@ RubyPort::getPort(const std::string &if_name, PortID idx) } // pass it along to our super class - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 922b3a973..20bc03a07 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -49,13 +49,13 @@ #include "mem/ruby/common/MachineID.hh" #include "mem/ruby/network/MessageBuffer.hh" #include "mem/ruby/system/RubySystem.hh" -#include "mem/mem_object.hh" #include "mem/tport.hh" #include "params/RubyPort.hh" +#include "sim/clocked_object.hh" class AbstractController; -class RubyPort : public MemObject +class RubyPort : public ClockedObject { public: class MemMasterPort : public QueuedMasterPort diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 35460438c..2aede349d 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -29,9 +29,9 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class RubyPort(MemObject): +class RubyPort(ClockedObject): type = 'RubyPort' abstract = True cxx_header = "mem/ruby/system/RubyPort.hh" diff --git a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py index 77ee60554..fa50c95dc 100644 --- a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py +++ b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py @@ -33,7 +33,6 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject from m5.objects.ReplacementPolicy import ReplacementPolicy class WeightedLRUReplacementPolicy(ReplacementPolicy): |