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| author | Daniel Sanchez <sanchezd@stanford.edu> | 2009-05-11 10:38:46 -0700 |
|---|---|---|
| committer | Daniel Sanchez <sanchezd@stanford.edu> | 2009-05-11 10:38:46 -0700 |
| commit | 93f2f69657d0a2420a2c86b71505e6d27e6e2a38 (patch) | |
| tree | 8022fec4e3f70b9fb777518d26116eb99b962f80 /src/mem/ruby/tester/DetermGETXGenerator.cc | |
| parent | ebf2f5aaddcb81ba39692b716ed9ad658df27cd8 (diff) | |
| download | gem5-93f2f69657d0a2420a2c86b71505e6d27e6e2a38.tar.xz | |
ruby: Working M5 interface and updated Ruby interface.
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>
RubyMemory is now both a driver for Ruby and a port for M5. Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
Diffstat (limited to 'src/mem/ruby/tester/DetermGETXGenerator.cc')
| -rw-r--r-- | src/mem/ruby/tester/DetermGETXGenerator.cc | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/mem/ruby/tester/DetermGETXGenerator.cc b/src/mem/ruby/tester/DetermGETXGenerator.cc index d496cbe3a..e4d8addd2 100644 --- a/src/mem/ruby/tester/DetermGETXGenerator.cc +++ b/src/mem/ruby/tester/DetermGETXGenerator.cc @@ -44,6 +44,7 @@ #include "mem/ruby/common/SubBlock.hh" #include "mem/ruby/tester/DeterministicDriver.hh" #include "mem/protocol/Chip.hh" +#include "mem/packet.hh" DetermGETXGenerator::DetermGETXGenerator(NodeID node, DeterministicDriver& driver) : m_driver(driver) @@ -137,7 +138,15 @@ void DetermGETXGenerator::pickAddress() void DetermGETXGenerator::initiateStore() { DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store"); - sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */)); + + Addr data_addr = m_address.getAddress(); + Request request(0, data_addr, 1, Flags<unsigned int>(), 3, 0, 0); + MemCmd::Command command; + command = MemCmd::WriteReq; + + Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID + + sequencer()->makeRequest(&pkt); } Sequencer* DetermGETXGenerator::sequencer() const |