merge

1 files changed, 65 insertions, 37 deletions

diff --git a/src/mem/ruby/tester/DetermInvGenerator.cc b/src/mem/ruby/tester/DetermInvGenerator.cc
index eebe18057..73ef8b66a 100644
--- a/src/mem/ruby/tester/DetermInvGenerator.cc
+++ b/src/mem/ruby/tester/DetermInvGenerator.cc
@@ -1,31 +1,58 @@
 
 /*
- * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
+    Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the
+    Wisconsin Multifacet Project.  Contact: gems@cs.wisc.edu
+    http://www.cs.wisc.edu/gems/
+
+    --------------------------------------------------------------------
+
+    This file is part of the Ruby Multiprocessor Memory System Simulator, 
+    a component of the Multifacet GEMS (General Execution-driven 
+    Multiprocessor Simulator) software toolset originally developed at 
+    the University of Wisconsin-Madison.
+
+    Ruby was originally developed primarily by Milo Martin and Daniel
+    Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj
+    Plakal.
+
+    Substantial further development of Multifacet GEMS at the
+    University of Wisconsin was performed by Alaa Alameldeen, Brad
+    Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper,
+    Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan,
+    Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, 
+    Min Xu, and Luke Yen.
+    --------------------------------------------------------------------
+
+    If your use of this software contributes to a published paper, we
+    request that you (1) cite our summary paper that appears on our
+    website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation
+    for your published paper to gems@cs.wisc.edu.
+
+    If you redistribute derivatives of this software, we request that
+    you notify us and either (1) ask people to register with us at our
+    website (http://www.cs.wisc.edu/gems/) or (2) collect registration
+    information and periodically send it to us.
+
+    --------------------------------------------------------------------
+
+    Multifacet GEMS is free software; you can redistribute it and/or
+    modify it under the terms of version 2 of the GNU General Public
+    License as published by the Free Software Foundation.
+
+    Multifacet GEMS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with the Multifacet GEMS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+    02111-1307, USA
+
+    The GNU General Public License is contained in the file LICENSE.
+
+### END HEADER ###
+*/
 
 /*
  * $Id$
@@ -36,10 +63,11 @@
 // then Invalidates them with a GETX.  The GETS and GETX request are generated one
 // at a time in round-robin fashion 0...1...2...etc.
 
+#include "mem/ruby/common/Global.hh"
 #include "mem/ruby/tester/DetermInvGenerator.hh"
 #include "mem/protocol/DetermInvGeneratorStatus.hh"
 #include "mem/ruby/tester/DeterministicDriver.hh"
-#include "mem/ruby/tester/Global_Tester.hh"
+#include "mem/ruby/tester/Tester_Globals.hh"
 //#include "DMAController.hh"
 #include "mem/ruby/libruby.hh"
 
@@ -75,7 +103,7 @@ void DetermInvGenerator::wakeup()
     } else { // I'll check again later
       m_driver.eventQueue->scheduleEvent(this, thinkTime());
     }
-  } else if (m_status == DetermInvGeneratorStatus_Load_Complete) {
+  } else if (m_status == DetermInvGeneratorStatus_Load_Complete) {    
     if (m_driver.isStoreReady(m_node, m_address))   {  // do a store in this transaction or start the next one
       if (m_driver.isLoadReady((0), m_address)) {  // everyone is in S for this address i.e. back to node 0
         m_status = DetermInvGeneratorStatus_Store_Pending;
@@ -98,13 +126,13 @@ void DetermInvGenerator::wakeup()
 void DetermInvGenerator::performCallback(NodeID proc, Address address)
 {
   assert(proc == m_node);
-  assert(address == m_address);
+  assert(address == m_address);  
 
   DEBUG_EXPR(TESTER_COMP, LowPrio, proc);
   DEBUG_EXPR(TESTER_COMP, LowPrio, m_status);
   DEBUG_EXPR(TESTER_COMP, LowPrio, address);
 
-  if (m_status == DetermInvGeneratorStatus_Load_Pending) {
+  if (m_status == DetermInvGeneratorStatus_Load_Pending) { 
     m_driver.recordLoadLatency(m_driver.eventQueue->getTime() - m_last_transition);
     //NodeID firstByte = data.readByte();  // dummy read
 
@@ -121,9 +149,9 @@ void DetermInvGenerator::performCallback(NodeID proc, Address address)
       m_driver.reportDone();
       m_status = DetermInvGeneratorStatus_Done;
       m_last_transition = m_driver.eventQueue->getTime();
-    }
+    } 
 
-  } else if (m_status == DetermInvGeneratorStatus_Store_Pending) {
+  } else if (m_status == DetermInvGeneratorStatus_Store_Pending) { 
     m_driver.recordStoreLatency(m_driver.eventQueue->getTime() - m_last_transition);
     //data.writeByte(m_node);
     m_driver.storeCompleted(m_node, address);  // advance the store queue
@@ -137,7 +165,7 @@ void DetermInvGenerator::performCallback(NodeID proc, Address address)
       m_driver.reportDone();
       m_status = DetermInvGeneratorStatus_Done;
       m_last_transition = m_driver.eventQueue->getTime();
-    }
+    }     
   } else {
     WARN_EXPR(m_status);
     ERROR_MSG("Invalid status");
@@ -174,7 +202,7 @@ void DetermInvGenerator::pickLoadAddress()
 void DetermInvGenerator::initiateLoad()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Load");
-  // sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, Address(0), 0 /* only 1 SMT thread */));
+  // sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, Address(0), 0 /* only 1 SMT thread */)); 
   uint8_t * read_data = new uint8_t[64];
 
   char name [] = "Sequencer_";
@@ -185,7 +213,7 @@ void DetermInvGenerator::initiateLoad()
 
   //delete [] read_data;
 
-  ASSERT(m_driver.requests.find(request_id) == m_driver.requests.end());
+  ASSERT(m_driver.requests.find(request_id) == m_driver.requests.end()); 
   m_driver.requests.insert(make_pair(request_id, make_pair(m_node, m_address)));
 
 }
@@ -193,7 +221,7 @@ void DetermInvGenerator::initiateLoad()
 void DetermInvGenerator::initiateStore()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store");
-  // sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, Address(0), 0 /* only 1 SMT thread */));
+  // sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, Address(0), 0 /* only 1 SMT thread */)); 
   uint8_t *write_data = new uint8_t[64];
   for(int i=0; i < 64; i++) {
       write_data[i] = m_node;
@@ -207,7 +235,7 @@ void DetermInvGenerator::initiateStore()
 
   //delete [] write_data;
 
-  ASSERT(m_driver.requests.find(request_id) == m_driver.requests.end());
+  ASSERT(m_driver.requests.find(request_id) == m_driver.requests.end()); 
   m_driver.requests.insert(make_pair(request_id, make_pair(m_node, m_address)));
 
 }