ruby: removed last level cache support

Removed the last level cache support and MOESI_hammer's dependency on it.
Replaces the LLC support with the more generic MachineType count.

4 files changed, 4 insertions, 38 deletions

diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
index 4d37b0007..0821201e7 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
@@ -31,8 +31,4 @@
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
 #include "mem/ruby/system/CacheMemory.hh"
 
-int getNumberOfLastLevelCaches()
-{
-  return CacheMemory::numberOfLastLevelCaches();
-}
 
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index 69424c414..5ffd0f295 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -42,6 +42,7 @@
 #include "mem/ruby/common/NetDest.hh"
 #include "mem/protocol/GenericMachineType.hh"
 #include "mem/ruby/system/DirectoryMemory.hh"
+#include "mem/protocol/MachineType.hh"
 
 #ifdef MACHINETYPE_L1Cache
 #define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache
@@ -67,9 +68,6 @@
 #define MACHINETYPE_DMA_ENUM MachineType_NUM
 #endif
 
-// used to determine the number of acks to wait for
-int getNumberOfLastLevelCaches();
-
 // used to determine the home directory
 // returns a value between 0 and total_directories_within_the_system
 inline
@@ -152,5 +150,8 @@ extern inline GenericMachineType ConvertMachToGenericMach(MachineType machType)
   }
 }
 
+extern inline int machineCount(MachineType machType) {
+    return MachineType_base_count(machType);
+}
 
 #endif  // COMPONENTMAPPINGFNS_H
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index 8c5112183..110dce2d0 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -28,9 +28,6 @@
 
 #include "mem/ruby/system/CacheMemory.hh"
 
-int CacheMemory::m_num_last_level_caches = 0;
-MachineType CacheMemory::m_last_level_machine_type = MachineType_FIRST;
-
 // ******************* Definitions *******************
 
 // Output operator definition
@@ -75,19 +72,6 @@ void CacheMemory::init()
     else
       assert(false);
 
-  m_num_last_level_caches = 
-    MachineType_base_count(MachineType_FIRST);
-#if 0
-  for (uint32 i=0; i<argv.size(); i+=2) {
-      if (m_last_level_machine_type < m_controller->getMachineType()) {
-        m_num_last_level_caches = 
-          MachineType_base_count(m_controller->getMachineType());
-        m_last_level_machine_type = 
-          m_controller->getMachineType();
-      } 
-  }
-#endif
-
   m_cache.setSize(m_cache_num_sets);
   m_locked.setSize(m_cache_num_sets);
   for (int i = 0; i < m_cache_num_sets; i++) {
@@ -112,13 +96,6 @@ CacheMemory::~CacheMemory()
   }
 }
 
-int
-CacheMemory::numberOfLastLevelCaches()
-{ 
-  return m_num_last_level_caches; 
-}
-
-
 void CacheMemory::printConfig(ostream& out)
 {
   out << "Cache config: " << m_cache_name << endl;
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index f70427f2d..74eb5d68d 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -106,8 +106,6 @@ public:
   AccessPermission getPermission(const Address& address) const;
   void changePermission(const Address& address, AccessPermission new_perm);
 
-  static int numberOfLastLevelCaches();
-
   int getLatency() const { return m_latency; }
 
   // Hook for checkpointing the contents of the cache
@@ -172,12 +170,6 @@ private:
   int m_cache_num_sets;
   int m_cache_num_set_bits;
   int m_cache_assoc;
-
-  static Vector< CacheMemory* > m_all_caches;
-  
-  static int m_num_last_level_caches;
-  static MachineType m_last_level_machine_type;
-
 };
 
 #endif //CACHEMEMORY_H