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authorAndreas Hansson <andreas.hansson@arm.com>2014-10-16 05:49:44 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-10-16 05:49:44 -0400
commit247586274724ea9f2a22a87747c9e074870d16a8 (patch)
tree0de83b50fe2856e3bc43eb9a24e2f767719ee2d5 /src/mem/ruby
parentdf973abef3a70074971375cfe52c46f53528c00e (diff)
downloadgem5-247586274724ea9f2a22a87747c9e074870d16a8.tar.xz
arch,x86,mem: Dynamically determine the ISA for Ruby store check
This patch makes the memory system ISA-agnostic by enabling the Ruby Sequencer to dynamically determine if it has to do a store check. To enable this check, the ISA is encoded as an enum, and the system is able to provide the ISA to the Sequencer at run time. --HG-- rename : src/arch/x86/insts/microldstop.hh => src/arch/x86/ldstflags.hh
Diffstat (limited to 'src/mem/ruby')
-rw-r--r--src/mem/ruby/system/RubyPort.cc3
-rw-r--r--src/mem/ruby/system/RubyPort.hh2
-rw-r--r--src/mem/ruby/system/Sequencer.cc18
3 files changed, 11 insertions, 12 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 71b08ebbb..b839e6646 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -52,13 +52,14 @@
RubyPort::RubyPort(const Params *p)
: MemObject(p), m_version(p->version), m_controller(NULL),
m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester),
+ system(p->system),
pioMasterPort(csprintf("%s.pio-master-port", name()), this),
pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
memMasterPort(csprintf("%s.mem-master-port", name()), this),
memSlavePort(csprintf("%s-mem-slave-port", name()), this,
p->ruby_system, p->access_phys_mem, -1),
gotAddrRanges(p->port_master_connection_count), drainManager(NULL),
- system(p->system), access_phys_mem(p->access_phys_mem)
+ access_phys_mem(p->access_phys_mem)
{
assert(m_version != -1);
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 12e97208f..648580246 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -182,6 +182,7 @@ class RubyPort : public MemObject
AbstractController* m_controller;
MessageBuffer* m_mandatory_q_ptr;
bool m_usingRubyTester;
+ System* system;
private:
void addToRetryList(MemSlavePort * port)
@@ -205,7 +206,6 @@ class RubyPort : public MemObject
std::vector<PioMasterPort *> master_ports;
DrainManager *drainManager;
- System* system;
//
// Based on similar code in the M5 bus. Stores pointers to those ports
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 8d9640a04..dcdaf6a6f 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -26,12 +26,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "arch/x86/ldstflags.hh"
#include "base/misc.hh"
#include "base/str.hh"
-#include "config/the_isa.hh"
-#if THE_ISA == X86_ISA
-#include "arch/x86/insts/microldstop.hh"
-#endif // X86_ISA
#include "cpu/testers/rubytest/RubyTester.hh"
#include "debug/MemoryAccess.hh"
#include "debug/ProtocolTrace.hh"
@@ -45,6 +42,7 @@
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/system/System.hh"
#include "mem/packet.hh"
+#include "sim/system.hh"
using namespace std;
@@ -630,13 +628,13 @@ Sequencer::makeRequest(PacketPtr pkt)
if (pkt->req->isInstFetch()) {
primary_type = secondary_type = RubyRequestType_IFETCH;
} else {
-#if THE_ISA == X86_ISA
- uint32_t flags = pkt->req->getFlags();
- bool storeCheck = flags &
- (TheISA::StoreCheck << TheISA::FlagShift);
-#else
bool storeCheck = false;
-#endif // X86_ISA
+ // only X86 need the store check
+ if (system->getArch() == Arch::X86ISA) {
+ uint32_t flags = pkt->req->getFlags();
+ storeCheck = flags &
+ (X86ISA::StoreCheck << X86ISA::FlagShift);
+ }
if (storeCheck) {
primary_type = RubyRequestType_RMW_Read;
secondary_type = RubyRequestType_ST;