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authorTony Gutierrez <anthony.gutierrez@amd.com>2016-02-18 10:50:16 -0500
committerTony Gutierrez <anthony.gutierrez@amd.com>2016-02-18 10:50:16 -0500
commit5a88f0931fa1e222ed3ac3aff4046721c593ee3e (patch)
treefac32dff574660c22b12ce0add4fcd1bbc8597c1 /src/mem/ruby
parenta28a234069a0c38bb75ba051ef82e7b4400f133a (diff)
downloadgem5-5a88f0931fa1e222ed3ac3aff4046721c593ee3e.tar.xz
ruby: move range change send from RubyPort to derived classes.
Diffstat (limited to 'src/mem/ruby')
-rw-r--r--src/mem/ruby/system/DMASequencer.cc3
-rw-r--r--src/mem/ruby/system/RubyPort.cc3
-rw-r--r--src/mem/ruby/system/RubyPort.hh3
3 files changed, 5 insertions, 4 deletions
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index fc2433a6c..6e708a927 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -46,6 +46,9 @@ DMASequencer::init()
RubyPort::init();
m_is_busy = false;
m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
+
+ for (const auto &s_port : slave_ports)
+ s_port->sendRangeChange();
}
RequestStatus
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index d4fc9e3fe..bf4002126 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -84,9 +84,6 @@ RubyPort::init()
{
assert(m_controller != NULL);
m_mandatory_q_ptr = m_controller->getMandatoryQueue();
-
- for (const auto &s_port : slave_ports)
- s_port->sendRangeChange();
}
BaseMasterPort &
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 6bd92b654..6c991c162 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -192,6 +192,8 @@ class RubyPort : public MemObject
bool m_usingRubyTester;
System* system;
+ std::vector<MemSlavePort *> slave_ports;
+
private:
bool onRetryList(MemSlavePort * port)
{
@@ -212,7 +214,6 @@ class RubyPort : public MemObject
/** Vector of M5 Ports attached to this Ruby port. */
typedef std::vector<MemSlavePort *>::iterator CpuPortIter;
- std::vector<MemSlavePort *> slave_ports;
std::vector<PioMasterPort *> master_ports;
//