ruby: Add support for address ranges in the directory

Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.

Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

9 files changed, 225 insertions, 100 deletions

diff --git a/src/mem/ruby/network/Network.cc b/src/mem/ruby/network/Network.cc
index e9b28a731..1761218b0 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -29,6 +41,7 @@
 #include "mem/ruby/network/Network.hh"
 
 #include "base/misc.hh"
+#include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/network/BasicLink.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
@@ -73,6 +86,15 @@ Network::Network(const Params *p)
         BasicExtLink *ext_link = (*i);
         AbstractController *abs_cntrl = ext_link->params()->ext_node;
         abs_cntrl->initNetworkPtr(this);
+        const AddrRangeList &ranges = abs_cntrl->getAddrRanges();
+        if (!ranges.empty()) {
+            MachineID mid = abs_cntrl->getMachineID();
+            AddrMapNode addr_map_node = {
+                .id = mid.getNum(),
+                .ranges = ranges
+            };
+            addrMap.emplace(mid.getType(), addr_map_node);
+        }
     }
 
     // Register a callback function for combining the statistics
@@ -172,3 +194,21 @@ Network::setFromNetQueue(NodeID id, bool ordered, int network_num,
     }
     m_fromNetQueues[id][network_num] = b;
 }
+
+NodeID
+Network::addressToNodeID(Addr addr, MachineType mtype)
+{
+    // Look through the address maps for entries with matching machine
+    // type to get the responsible node for this address.
+    const auto &matching_ranges = addrMap.equal_range(mtype);
+    for (auto it = matching_ranges.first; it != matching_ranges.second; it++) {
+        AddrMapNode &node = it->second;
+        auto &ranges = node.ranges;
+        for (AddrRange &range: ranges) {
+            if (range.contains(addr)) {
+                return node.id;
+            }
+        }
+    }
+    return MachineType_base_count(mtype);
+}
diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh
index 4c0d4edfc..7f5ed2aae 100644
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -42,13 +54,17 @@
 
 #include <iostream>
 #include <string>
+#include <unordered_map>
 #include <vector>
 
+#include "base/addr_range.hh"
+#include "base/types.hh"
+#include "mem/packet.hh"
 #include "mem/protocol/LinkDirection.hh"
 #include "mem/protocol/MessageSizeType.hh"
+#include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/common/TypeDefines.hh"
 #include "mem/ruby/network/Topology.hh"
-#include "mem/packet.hh"
 #include "params/RubyNetwork.hh"
 #include "sim/clocked_object.hh"
 
@@ -102,6 +118,20 @@ class Network : public ClockedObject
     virtual uint32_t functionalWrite(Packet *pkt)
     { fatal("Functional write not implemented.\n"); }
 
+    /**
+     * Map an address to the correct NodeID
+     *
+     * This function traverses the global address map to find the
+     * NodeID that corresponds to the given address and the type of
+     * the destination. For example for a request to a directory this
+     * function will return the NodeID of the right directory.
+     *
+     * @param the destination address
+     * @param the type of the destination
+     * @return the NodeID of the destination
+     */
+    NodeID addressToNodeID(Addr addr, MachineType mtype);
+
   protected:
     // Private copy constructor and assignment operator
     Network(const Network& obj);
@@ -137,6 +167,13 @@ class Network : public ClockedObject
 
         void process() {ctr->collateStats();}
     };
+
+    // Global address map
+    struct AddrMapNode {
+        NodeID id;
+        AddrRangeList ranges;
+    };
+    std::unordered_multimap<MachineType, AddrMapNode> addrMap;
 };
 
 inline std::ostream&
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 19dca9028..0bc88eefa 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2011-2014 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -43,7 +55,8 @@ AbstractController::AbstractController(const Params *p)
       m_number_of_TBEs(p->number_of_TBEs),
       m_transitions_per_cycle(p->transitions_per_cycle),
       m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
-      memoryPort(csprintf("%s.memory", name()), this, "")
+      memoryPort(csprintf("%s.memory", name()), this, ""),
+      addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
 {
     if (m_version == 0) {
         // Combine the statistics from all controllers
@@ -347,6 +360,14 @@ AbstractController::recvTimingResp(PacketPtr pkt)
     delete pkt;
 }
 
+MachineID
+AbstractController::mapAddressToMachine(Addr addr, MachineType mtype) const
+{
+    NodeID node = m_net_ptr->addressToNodeID(addr, mtype);
+    MachineID mach = {mtype, node};
+    return mach;
+}
+
 bool
 AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt)
 {
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index e4562145f..354dc80aa 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -33,8 +45,12 @@
 #include <iostream>
 #include <string>
 
+#include "base/addr_range.hh"
 #include "base/callback.hh"
+#include "mem/mem_object.hh"
+#include "mem/packet.hh"
 #include "mem/protocol/AccessPermission.hh"
+#include "mem/qport.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/common/DataBlock.hh"
@@ -42,10 +58,7 @@
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/network/MessageBuffer.hh"
 #include "mem/ruby/system/CacheRecorder.hh"
-#include "mem/packet.hh"
-#include "mem/qport.hh"
 #include "params/RubyController.hh"
-#include "mem/mem_object.hh"
 
 class Network;
 class GPUCoalescer;
@@ -123,6 +136,8 @@ class AbstractController : public MemObject, public Consumer
                                  const DataBlock &block, int size);
     void recvTimingResp(PacketPtr pkt);
 
+    const AddrRangeList &getAddrRanges() const { return addrRanges; }
+
   public:
     MachineID getMachineID() const { return m_machineID; }
 
@@ -130,6 +145,21 @@ class AbstractController : public MemObject, public Consumer
     Stats::Histogram& getDelayVCHist(uint32_t index)
     { return *(m_delayVCHistogram[index]); }
 
+    /**
+     * Map an address to the correct MachineID
+     *
+     * This function querries the network for the NodeID of the
+     * destination for a given request using its address and the type
+     * of the destination. For example for a request with a given
+     * address to a directory it will return the MachineID of the
+     * authorative directory.
+     *
+     * @param the destination address
+     * @param the type of the destination
+     * @return the MachineID of the destination
+     */
+    MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
+
   protected:
     //! Profiles original cache requests including PUTs
     void profileRequest(const std::string &request);
@@ -223,6 +253,10 @@ class AbstractController : public MemObject, public Consumer
         SenderState(MachineID _id) : id(_id)
         {}
     };
+
+  private:
+    /** The address range to which the controller responds on the CPU side. */
+    const AddrRangeList addrRanges;
 };
 
 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index ba7d17c7c..39a0ea912 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2009 Advanced Micro Devices, Inc.
 # All rights reserved.
 #
@@ -37,6 +49,8 @@ class RubyController(MemObject):
     cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
     abstract = True
     version = Param.Int("")
+    addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this "
+                                        "controller responds to")
     cluster_id = Param.UInt32(0, "Id of this controller's cluster")
 
     transitions_per_cycle = \
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index cdedc2e14..dfc2c73fc 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -35,46 +35,6 @@
 #include "mem/ruby/common/NetDest.hh"
 #include "mem/ruby/structures/DirectoryMemory.hh"
 
-// used to determine the home directory
-// returns a value between 0 and total_directories_within_the_system
-inline NodeID
-map_Address_to_DirectoryNode(Addr addr)
-{
-    return DirectoryMemory::mapAddressToDirectoryVersion(addr);
-}
-
-inline NodeID
-map_Address_to_TCCdirNode(Addr addr)
-{
-    return DirectoryMemory::mapAddressToDirectoryVersion(addr);
-}
-
-// used to determine the home directory
-// returns a value between 0 and total_directories_within_the_system
-inline MachineID
-map_Address_to_Directory(Addr addr)
-{
-    MachineID mach =
-        {MachineType_Directory, map_Address_to_DirectoryNode(addr)};
-    return mach;
-}
-
-inline MachineID
-map_Address_to_RegionDir(Addr addr)
-{
-    MachineID mach = {MachineType_RegionDir,
-                      map_Address_to_DirectoryNode(addr)};
-    return mach;
-}
-
-inline MachineID
-map_Address_to_TCCdir(Addr addr)
-{
-    MachineID mach =
-        {MachineType_TCCdir, map_Address_to_TCCdirNode(addr)};
-    return mach;
-}
-
 inline NetDest
 broadcast(MachineType type)
 {
diff --git a/src/mem/ruby/structures/DirectoryMemory.cc b/src/mem/ruby/structures/DirectoryMemory.cc
index ee77931d7..551e3f57f 100644
--- a/src/mem/ruby/structures/DirectoryMemory.cc
+++ b/src/mem/ruby/structures/DirectoryMemory.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * Copyright (c) 2017 Google Inc.
  * All rights reserved.
@@ -31,6 +43,7 @@
 
 #include "mem/ruby/structures/DirectoryMemory.hh"
 
+#include "base/addr_range.hh"
 #include "base/intmath.hh"
 #include "debug/RubyCache.hh"
 #include "debug/RubyStats.hh"
@@ -40,25 +53,15 @@
 
 using namespace std;
 
-int DirectoryMemory::m_num_directories = 0;
-int DirectoryMemory::m_num_directories_bits = 0;
-int DirectoryMemory::m_numa_high_bit = 0;
-
 DirectoryMemory::DirectoryMemory(const Params *p)
-    : SimObject(p)
+    : SimObject(p), addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
 {
-    m_version = p->version;
-    // In X86, there is an IO gap in the 3-4GB range.
-    if (p->system->getArch() == Arch::X86ISA && p->size > 0xc0000000){
-        // We need to add 1GB to the size for the gap
-        m_size_bytes = p->size + 0x40000000;
-    }
-    else {
-        m_size_bytes = p->size;
+    m_size_bytes = 0;
+    for (const auto &r: addrRanges) {
+        m_size_bytes += r.size();
     }
     m_size_bits = floorLog2(m_size_bytes);
     m_num_entries = 0;
-    m_numa_high_bit = p->numa_high_bit;
 }
 
 void
@@ -68,14 +71,6 @@ DirectoryMemory::init()
     m_entries = new AbstractEntry*[m_num_entries];
     for (int i = 0; i < m_num_entries; i++)
         m_entries[i] = NULL;
-
-    m_num_directories++;
-    m_num_directories_bits = ceilLog2(m_num_directories);
-
-    if (m_numa_high_bit == 0) {
-        m_numa_high_bit = RubySystem::getMemorySizeBits() - 1;
-    }
-    assert(m_numa_high_bit != 0);
 }
 
 DirectoryMemory::~DirectoryMemory()
@@ -89,37 +84,29 @@ DirectoryMemory::~DirectoryMemory()
     delete [] m_entries;
 }
 
-uint64_t
-DirectoryMemory::mapAddressToDirectoryVersion(Addr address)
-{
-    if (m_num_directories_bits == 0)
-        return 0;
-
-    uint64_t ret = bitSelect(address,
-                           m_numa_high_bit - m_num_directories_bits + 1,
-                           m_numa_high_bit);
-    return ret;
-}
-
 bool
 DirectoryMemory::isPresent(Addr address)
 {
-    bool ret = (mapAddressToDirectoryVersion(address) == m_version);
-    return ret;
+    for (const auto& r: addrRanges) {
+        if (r.contains(address)) {
+            return true;
+        }
+    }
+    return false;
 }
 
 uint64_t
 DirectoryMemory::mapAddressToLocalIdx(Addr address)
 {
-    uint64_t ret;
-    if (m_num_directories_bits > 0) {
-        ret = bitRemove(address, m_numa_high_bit - m_num_directories_bits + 1,
-                        m_numa_high_bit);
-    } else {
-        ret = address;
+    uint64_t ret = 0;
+    for (const auto& r: addrRanges) {
+        if (r.contains(address)) {
+            ret += r.getOffset(address);
+            break;
+        }
+        ret += r.size();
     }
-
-    return ret >> (RubySystem::getBlockSizeBits());
+    return ret >> RubySystem::getBlockSizeBits();
 }
 
 AbstractEntry*
diff --git a/src/mem/ruby/structures/DirectoryMemory.hh b/src/mem/ruby/structures/DirectoryMemory.hh
index 98403808b..36defd5e9 100644
--- a/src/mem/ruby/structures/DirectoryMemory.hh
+++ b/src/mem/ruby/structures/DirectoryMemory.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -32,6 +44,7 @@
 #include <iostream>
 #include <string>
 
+#include "base/addr_range.hh"
 #include "mem/protocol/DirectoryRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
@@ -47,8 +60,18 @@ class DirectoryMemory : public SimObject
 
     void init();
 
+    /**
+     * Return the index in the directory based on an address
+     *
+     * This function transforms an address which belongs to a not
+     * necessarily continuous vector of address ranges into a flat
+     * address that we use to index in the directory
+     *
+     * @param an input address
+     * @return the corresponding index in the directory
+     *
+     */
     uint64_t mapAddressToLocalIdx(Addr address);
-    static uint64_t mapAddressToDirectoryVersion(Addr address);
 
     uint64_t getSize() { return m_size_bytes; }
 
@@ -72,11 +95,12 @@ class DirectoryMemory : public SimObject
     uint64_t m_size_bytes;
     uint64_t m_size_bits;
     uint64_t m_num_entries;
-    int m_version;
 
-    static int m_num_directories;
-    static int m_num_directories_bits;
-    static int m_numa_high_bit;
+    /**
+     * The address range for which the directory responds. Normally
+     * this is all possible memory addresses.
+     */
+    const AddrRangeList addrRanges;
 };
 
 inline std::ostream&
diff --git a/src/mem/ruby/structures/DirectoryMemory.py b/src/mem/ruby/structures/DirectoryMemory.py
index 2518380b2..ab9c7235f 100644
--- a/src/mem/ruby/structures/DirectoryMemory.py
+++ b/src/mem/ruby/structures/DirectoryMemory.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2009 Advanced Micro Devices, Inc.
 # All rights reserved.
 #
@@ -35,9 +47,5 @@ class RubyDirectoryMemory(SimObject):
     type = 'RubyDirectoryMemory'
     cxx_class = 'DirectoryMemory'
     cxx_header = "mem/ruby/structures/DirectoryMemory.hh"
-    version = Param.Int(0, "")
-    size = Param.MemorySize("1GB", "capacity in bytes")
-    # the default value of the numa high bit is specified in the command line
-    # option and must be passed into the directory memory sim object
-    numa_high_bit = Param.Int("numa high bit")
-    system = Param.System(Parent.any, "system object")
+    addr_ranges = VectorParam.AddrRange(
+        Parent.addr_ranges, "Address range this directory responds to")