diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2015-10-12 04:08:01 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-10-12 04:08:01 -0400 |
commit | 2ac04c11accb46f92cf7f2b7abe40404dbf8c5d6 (patch) | |
tree | 368b579a0b45840a5248fca568f89a8ea7ca9d49 /src/mem/ruby | |
parent | 22c04190c607b9360d9a23548f8a54e83cf0e74a (diff) | |
download | gem5-2ac04c11accb46f92cf7f2b7abe40404dbf8c5d6.tar.xz |
misc: Add explicit overrides and fix other clang >= 3.5 issues
This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.
As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
Diffstat (limited to 'src/mem/ruby')
-rw-r--r-- | src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py | 2 | ||||
-rw-r--r-- | src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc | 2 | ||||
-rw-r--r-- | src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh | 1 | ||||
-rw-r--r-- | src/mem/ruby/structures/RubyMemoryControl.hh | 10 | ||||
-rw-r--r-- | src/mem/ruby/system/DMASequencer.hh | 4 | ||||
-rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 6 | ||||
-rw-r--r-- | src/mem/ruby/system/RubySystem.hh | 8 |
7 files changed, 15 insertions, 18 deletions
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py index 14c3f543c..4a957b66e 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py @@ -42,8 +42,6 @@ class NetworkLink_d(ClockedObject): "virtual channels per virtual network") virt_nets = Param.Int(Parent.number_of_virtual_networks, "number of virtual networks") - channel_width = Param.Int(Parent.bandwidth_factor, - "channel width == bw factor") class CreditLink_d(NetworkLink_d): type = 'CreditLink_d' diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc index 8d9acd433..60c7ca3f4 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc @@ -33,7 +33,7 @@ NetworkLink_d::NetworkLink_d(const Params *p) : ClockedObject(p), Consumer(this), m_id(p->link_id), - m_latency(p->link_latency), channel_width(p->channel_width), + m_latency(p->link_latency), linkBuffer(new flitBuffer_d()), link_consumer(nullptr), link_srcQueue(nullptr), m_link_utilized(0), m_vc_load(p->vcs_per_vnet * p->virt_nets) diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh index ad9fef2f4..be937f093 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh @@ -69,7 +69,6 @@ class NetworkLink_d : public ClockedObject, public Consumer private: const int m_id; const Cycles m_latency; - const int channel_width; flitBuffer_d *linkBuffer; Consumer *link_consumer; diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh index 75fe71dfb..cd777f5e7 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.hh +++ b/src/mem/ruby/structures/RubyMemoryControl.hh @@ -53,15 +53,15 @@ class RubyMemoryControl : public AbstractMemory, public Consumer public: typedef RubyMemoryControlParams Params; RubyMemoryControl(const Params *p); - void init(); + void init() override; void reset(); ~RubyMemoryControl(); virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; DrainState drain() override; - void wakeup(); + void wakeup() override; void setDescription(const std::string& name) { m_description = name; }; std::string getDescription() { return m_description; }; @@ -72,8 +72,8 @@ class RubyMemoryControl : public AbstractMemory, public Consumer void enqueueMemRef(MemoryNode *memRef); bool areNSlotsAvailable(int n) { return true; }; // infinite queue length - void print(std::ostream& out) const; - void regStats(); + void print(std::ostream& out) const override; + void regStats() override; const int getBank(const Addr addr) const; const int getRank(const Addr addr) const; diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh index 1d5451f6e..34f9be34c 100644 --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -60,7 +60,7 @@ class DMASequencer : public MemObject public: typedef DMASequencerParams Params; DMASequencer(const Params *); - void init(); + void init() override; RubySystem *m_ruby_system; public: @@ -95,7 +95,7 @@ class DMASequencer : public MemObject }; BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; /* external interface */ RequestStatus makeRequest(PacketPtr pkt); diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 98fab8c4e..58d2558dd 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -143,12 +143,12 @@ class RubyPort : public MemObject RubyPort(const Params *p); virtual ~RubyPort() {} - void init(); + void init() override; BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; virtual RequestStatus makeRequest(PacketPtr pkt) = 0; virtual int outstandingCount() const = 0; diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh index 23974e924..e396dce64 100644 --- a/src/mem/ruby/system/RubySystem.hh +++ b/src/mem/ruby/system/RubySystem.hh @@ -89,16 +89,16 @@ class RubySystem : public ClockedObject return m_profiler; } - void regStats() { m_profiler->regStats(name()); } + void regStats() override { m_profiler->regStats(name()); } void collateStats() { m_profiler->collateStats(); } - void resetStats(); + void resetStats() override; - void memWriteback(); + void memWriteback() override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; void drainResume() override; void process(); - void startup(); + void startup() override; bool functionalRead(Packet *ptr); bool functionalWrite(Packet *ptr); |