MOESI_hammer: break down miss latency stalled cycles

This patch tracks the number of cycles a transaction is delayed at different
points of the request-forward-response loop.

4 files changed, 187 insertions, 4 deletions

diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index 753fdd230..a42d919f7 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -286,6 +286,35 @@ Profiler::printStats(ostream& out, bool short_stats)
             }
         }
 
+        out << "miss_latency_wCC_issue_to_initial_request: " 
+            << m_wCCIssueToInitialRequestHistogram << endl;
+        out << "miss_latency_wCC_initial_forward_request: " 
+            << m_wCCInitialRequestToForwardRequestHistogram << endl;
+        out << "miss_latency_wCC_forward_to_first_response: " 
+            << m_wCCForwardRequestToFirstResponseHistogram << endl;
+        out << "miss_latency_wCC_first_response_to_completion: " 
+            << m_wCCFirstResponseToCompleteHistogram << endl;
+        out << "imcomplete_wCC_Times: " << m_wCCIncompleteTimes << endl;
+        out << "miss_latency_dir_issue_to_initial_request: " 
+            << m_dirIssueToInitialRequestHistogram << endl;
+        out << "miss_latency_dir_initial_forward_request: " 
+            << m_dirInitialRequestToForwardRequestHistogram << endl;
+        out << "miss_latency_dir_forward_to_first_response: " 
+            << m_dirForwardRequestToFirstResponseHistogram << endl;
+        out << "miss_latency_dir_first_response_to_completion: " 
+            << m_dirFirstResponseToCompleteHistogram << endl;
+        out << "imcomplete_dir_Times: " << m_dirIncompleteTimes << endl;
+
+        for (int i = 0; i < m_missMachLatencyHistograms.size(); i++) {
+            for (int j = 0; j < m_missMachLatencyHistograms[i].size(); j++) {
+                if (m_missMachLatencyHistograms[i][j].size() > 0) {
+                    out << "miss_latency_" << RubyRequestType(i) 
+                        << "_" << GenericMachineType(j) << ": "
+                        << m_missMachLatencyHistograms[i][j] << endl;
+                }
+            }
+        }
+
         out << endl;
 
         out << "All Non-Zero Cycle SW Prefetch Requests" << endl;
@@ -454,7 +483,24 @@ Profiler::clearStats()
     for (int i = 0; i < m_machLatencyHistograms.size(); i++) {
         m_machLatencyHistograms[i].clear(200);
     }
+    m_missMachLatencyHistograms.resize(RubyRequestType_NUM);
+    for (int i = 0; i < m_missLatencyHistograms.size(); i++) {
+        m_missMachLatencyHistograms[i].resize(GenericMachineType_NUM+1);
+        for (int j = 0; j < m_missMachLatencyHistograms[i].size(); j++) {
+            m_missMachLatencyHistograms[i][j].clear(200);
+        }
+    }
     m_allMissLatencyHistogram.clear(200);
+    m_wCCIssueToInitialRequestHistogram.clear(200);
+    m_wCCInitialRequestToForwardRequestHistogram.clear(200);
+    m_wCCForwardRequestToFirstResponseHistogram.clear(200);
+    m_wCCFirstResponseToCompleteHistogram.clear(200);
+    m_wCCIncompleteTimes = 0;
+    m_dirIssueToInitialRequestHistogram.clear(200);
+    m_dirInitialRequestToForwardRequestHistogram.clear(200);
+    m_dirForwardRequestToFirstResponseHistogram.clear(200);
+    m_dirFirstResponseToCompleteHistogram.clear(200);
+    m_dirIncompleteTimes = 0;
 
     m_SWPrefetchLatencyHistograms.resize(CacheRequestType_NUM);
     for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) {
@@ -581,6 +627,59 @@ Profiler::missLatency(Time cycles,
     m_allMissLatencyHistogram.add(cycles);
     m_missLatencyHistograms[type].add(cycles);
     m_machLatencyHistograms[respondingMach].add(cycles);
+    m_missMachLatencyHistograms[type][respondingMach].add(cycles);
+}
+
+void
+Profiler::missLatencyWcc(Time issuedTime,
+                         Time initialRequestTime,
+                         Time forwardRequestTime,
+                         Time firstResponseTime,
+                         Time completionTime)
+{
+    if ((issuedTime <= initialRequestTime) &&
+        (initialRequestTime <= forwardRequestTime) &&
+        (forwardRequestTime <= firstResponseTime) &&
+        (firstResponseTime <= completionTime)) {
+        m_wCCIssueToInitialRequestHistogram.add(initialRequestTime - issuedTime);
+        
+        m_wCCInitialRequestToForwardRequestHistogram.add(forwardRequestTime - 
+                                                         initialRequestTime);
+        
+        m_wCCForwardRequestToFirstResponseHistogram.add(firstResponseTime - 
+                                                        forwardRequestTime);
+        
+        m_wCCFirstResponseToCompleteHistogram.add(completionTime - 
+                                                  firstResponseTime);
+    } else {
+        m_wCCIncompleteTimes++;
+    }
+}
+
+void
+Profiler::missLatencyDir(Time issuedTime,
+                         Time initialRequestTime,
+                         Time forwardRequestTime,
+                         Time firstResponseTime,
+                         Time completionTime)
+{
+    if ((issuedTime <= initialRequestTime) &&
+        (initialRequestTime <= forwardRequestTime) &&
+        (forwardRequestTime <= firstResponseTime) &&
+        (firstResponseTime <= completionTime)) {
+        m_dirIssueToInitialRequestHistogram.add(initialRequestTime - issuedTime);
+        
+        m_dirInitialRequestToForwardRequestHistogram.add(forwardRequestTime - 
+                                                         initialRequestTime);
+        
+        m_dirForwardRequestToFirstResponseHistogram.add(firstResponseTime - 
+                                                        forwardRequestTime);
+        
+        m_dirFirstResponseToCompleteHistogram.add(completionTime - 
+                                                  firstResponseTime);
+    } else {
+        m_dirIncompleteTimes++;
+    }
 }
 
 // non-zero cycle prefetch request
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index de9834f05..3a11f0596 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -138,6 +138,18 @@ class Profiler : public SimObject, public Consumer
                      RubyRequestType type,
                      const GenericMachineType respondingMach);
 
+    void missLatencyWcc(Time issuedTime,
+                        Time initialRequestTime,
+                        Time forwardRequestTime,
+                        Time firstResponseTime,
+                        Time completionTime);
+    
+    void missLatencyDir(Time issuedTime,
+                        Time initialRequestTime,
+                        Time forwardRequestTime,
+                        Time firstResponseTime,
+                        Time completionTime);
+    
     void swPrefetchLatency(Time t, 
                            CacheRequestType type,
                            const GenericMachineType respondingMach);
@@ -200,6 +212,18 @@ class Profiler : public SimObject, public Consumer
 
     std::vector<Histogram> m_missLatencyHistograms;
     std::vector<Histogram> m_machLatencyHistograms;
+    std::vector< std::vector<Histogram> > m_missMachLatencyHistograms;
+    Histogram m_wCCIssueToInitialRequestHistogram;
+    Histogram m_wCCInitialRequestToForwardRequestHistogram;
+    Histogram m_wCCForwardRequestToFirstResponseHistogram;
+    Histogram m_wCCFirstResponseToCompleteHistogram;
+    int64 m_wCCIncompleteTimes;
+    Histogram m_dirIssueToInitialRequestHistogram;
+    Histogram m_dirInitialRequestToForwardRequestHistogram;
+    Histogram m_dirForwardRequestToFirstResponseHistogram;
+    Histogram m_dirFirstResponseToCompleteHistogram;
+    int64 m_dirIncompleteTimes;
+
     Histogram m_allMissLatencyHistogram;
 
     Histogram m_allSWPrefetchLatencyHistogram;
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 175bb6721..74b6355e8 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -357,6 +357,17 @@ Sequencer::writeCallback(const Address& address,
                          GenericMachineType mach, 
                          DataBlock& data)
 {
+    writeCallback(address, mach, data, 0, 0, 0);
+}
+
+void
+Sequencer::writeCallback(const Address& address,
+                         GenericMachineType mach, 
+                         DataBlock& data,
+                         Time initialRequestTime,
+                         Time forwardRequestTime,
+                         Time firstResponseTime)
+{
     assert(address == line_address(address));
     assert(m_writeRequestTable.count(line_address(address)));
 
@@ -385,7 +396,8 @@ Sequencer::writeCallback(const Address& address,
         m_controller->unblock(address);
     }
 
-    hitCallback(request, mach, data, success);
+    hitCallback(request, mach, data, success, 
+                initialRequestTime, forwardRequestTime, firstResponseTime);
 }
 
 void
@@ -399,6 +411,17 @@ Sequencer::readCallback(const Address& address,
                         GenericMachineType mach,
                         DataBlock& data)
 {
+    readCallback(address, mach, data, 0, 0, 0);
+}
+
+void
+Sequencer::readCallback(const Address& address,
+                        GenericMachineType mach,
+                        DataBlock& data,
+                        Time initialRequestTime,
+                        Time forwardRequestTime,
+                        Time firstResponseTime)
+{
     assert(address == line_address(address));
     assert(m_readRequestTable.count(line_address(address)));
 
@@ -413,14 +436,18 @@ Sequencer::readCallback(const Address& address,
            (request->ruby_request.type == RubyRequestType_RMW_Read) ||
            (request->ruby_request.type == RubyRequestType_IFETCH));
 
-    hitCallback(request, mach, data, true);
+    hitCallback(request, mach, data, true, 
+                initialRequestTime, forwardRequestTime, firstResponseTime);
 }
 
 void
 Sequencer::hitCallback(SequencerRequest* srequest,
                        GenericMachineType mach,
                        DataBlock& data,
-                       bool success)
+                       bool success,
+                       Time initialRequestTime,
+                       Time forwardRequestTime,
+                       Time firstResponseTime)
 {
     const RubyRequest & ruby_request = srequest->ruby_request;
     Address request_address(ruby_request.paddr);
@@ -445,6 +472,22 @@ Sequencer::hitCallback(SequencerRequest* srequest,
     if (miss_latency != 0) {
         g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
 
+        if (mach == GenericMachineType_L1Cache_wCC) {
+            g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
+                                                   initialRequestTime,
+                                                   forwardRequestTime,
+                                                   firstResponseTime,
+                                                   g_eventQueue_ptr->getTime());
+        }
+
+        if (mach == GenericMachineType_Directory) {
+            g_system_ptr->getProfiler()->missLatencyDir(issued_time,
+                                                   initialRequestTime,
+                                                   forwardRequestTime,
+                                                   firstResponseTime,
+                                                   g_eventQueue_ptr->getTime());
+        }
+
         if (Debug::getProtocolTrace()) {
             if (success) {
                 g_system_ptr->getProfiler()->
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index fecfc9a1a..4ab85dac8 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -80,12 +80,26 @@ class Sequencer : public RubyPort, public Consumer
                        GenericMachineType mach, 
                        DataBlock& data);
 
+    void writeCallback(const Address& address, 
+                       GenericMachineType mach, 
+                       DataBlock& data,
+                       Time initialRequestTime,
+                       Time forwardRequestTime,
+                       Time firstResponseTime);
+
     void readCallback(const Address& address, DataBlock& data);
 
     void readCallback(const Address& address, 
                       GenericMachineType mach, 
                       DataBlock& data);
 
+    void readCallback(const Address& address, 
+                      GenericMachineType mach, 
+                      DataBlock& data,
+                      Time initialRequestTime,
+                      Time forwardRequestTime,
+                      Time firstResponseTime);
+
     RequestStatus makeRequest(const RubyRequest & request);
     RequestStatus getRequestStatus(const RubyRequest& request);
     bool empty() const;
@@ -106,7 +120,10 @@ class Sequencer : public RubyPort, public Consumer
     void hitCallback(SequencerRequest* request, 
                      GenericMachineType mach,
                      DataBlock& data,
-                     bool success);
+                     bool success,
+                     Time initialRequestTime,
+                     Time forwardRequestTime,
+                     Time firstResponseTime);
 
     bool insertRequest(SequencerRequest* request);