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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-07 07:38:53 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-07 07:38:53 -0600 |
| commit | 10c2e8ae9ae3f8f41f88fce7de4c2946d23a98fc (patch) | |
| tree | 0a135bfaa2a3c4d965286e63a21b83e4d38b0d00 /src/mem/ruby | |
| parent | ce941fd2ae2908dd0261132f35ab90e82c07b6b7 (diff) | |
| download | gem5-10c2e8ae9ae3f8f41f88fce7de4c2946d23a98fc.tar.xz | |
Ruby Cache: Add param for marking caches as instruction only
Diffstat (limited to 'src/mem/ruby')
| -rw-r--r-- | src/mem/ruby/system/Cache.py | 1 | ||||
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.cc | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py index ab3ec4b29..79ab9b070 100644 --- a/src/mem/ruby/system/Cache.py +++ b/src/mem/ruby/system/Cache.py @@ -39,3 +39,4 @@ class RubyCache(SimObject): assoc = Param.Int(""); replacement_policy = Param.String("PSEUDO_LRU", ""); start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line"); + is_icache = Param.Bool(False, "is instruction only cache"); diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index fbf303ed8..1564128d3 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -55,6 +55,7 @@ CacheMemory::CacheMemory(const Params *p) m_policy = p->replacement_policy; m_profiler_ptr = new CacheProfiler(name()); m_start_index_bit = p->start_index_bit; + m_is_instruction_only_cache = p->is_icache; } void |