ruby: Cleaned up sequencer. Removed LogTM specific code.

9 files changed, 17 insertions, 173 deletions

diff --git a/src/mem/ruby/recorder/TraceRecord.cc b/src/mem/ruby/recorder/TraceRecord.cc
index 3116edf93..fd5f25ab9 100644
--- a/src/mem/ruby/recorder/TraceRecord.cc
+++ b/src/mem/ruby/recorder/TraceRecord.cc
@@ -78,7 +78,7 @@ void TraceRecord::issueRequest() const
   Sequencer* sequencer_ptr = chip_ptr->getSequencer((m_node_num/RubyConfig::numberofSMTThreads())%RubyConfig::numberOfProcsPerChip());
   assert(sequencer_ptr != NULL);
 
-  CacheMsg request(m_data_address, m_data_address, m_type, m_pc_address, AccessModeType_UserMode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */, 0, false);
+  CacheMsg request(m_data_address, m_data_address, m_type, m_pc_address, AccessModeType_UserMode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */);
 
   // Clear out the sequencer
   while (!sequencer_ptr->empty()) {
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 5cf4a3acf..43b0df1b1 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -47,12 +47,6 @@
 #include "Protocol.hh"
 #include "Map.hh"
 #include "interface.hh"
-//#include "XactCommitArbiter.hh"
-// #include "TransactionInterfaceManager.hh"
-//#include "TransactionVersionManager.hh"
-//#include "LazyTransactionVersionManager.hh"
-
-//#define XACT_MGR g_system_ptr->getChip(m_chip_ptr->getID())->getTransactionInterfaceManager(m_version)
 
 Sequencer::Sequencer(AbstractChip* chip_ptr, int version) {
   m_chip_ptr = chip_ptr;
@@ -158,11 +152,8 @@ int Sequencer::getNumberOutstandingDemand(){
     Vector<Address> keys = m_readRequestTable_ptr[p]->keys();
     for (int i=0; i< keys.size(); i++) {
       CacheMsg& request = m_readRequestTable_ptr[p]->lookup(keys[i]);
-      // don't count transactional begin/commit requests
-      if(request.getType() != CacheRequestType_BEGIN_XACT && request.getType() != CacheRequestType_COMMIT_XACT){
-        if(request.getPrefetch() == PrefetchBit_No){
-          total_demand++;
-        }
+      if(request.getPrefetch() == PrefetchBit_No){
+        total_demand++;
       }
     }
 
@@ -394,8 +385,6 @@ bool Sequencer::insertRequest(const CacheMsg& request) {
   }
 
   if ((request.getType() == CacheRequestType_ST) ||
-      (request.getType() == CacheRequestType_ST_XACT) ||
-      (request.getType() == CacheRequestType_LDX_XACT) ||
       (request.getType() == CacheRequestType_ATOMIC)) {
     if (m_writeRequestTable_ptr[thread]->exist(line_address(request.getAddress()))) {
       m_writeRequestTable_ptr[thread]->lookup(line_address(request.getAddress())) = request;
@@ -436,8 +425,6 @@ void Sequencer::removeRequest(const CacheMsg& request) {
   assert(m_outstanding_count == total_outstanding);
 
   if ((request.getType() == CacheRequestType_ST) ||
-      (request.getType() == CacheRequestType_ST_XACT) ||
-      (request.getType() == CacheRequestType_LDX_XACT) ||
       (request.getType() == CacheRequestType_ATOMIC)) {
     m_writeRequestTable_ptr[thread]->deallocate(line_address(request.getAddress()));
   } else {
@@ -497,8 +484,6 @@ void Sequencer::writeCallback(const Address& address, DataBlock& data, GenericMa
   removeRequest(request);
 
   assert((request.getType() == CacheRequestType_ST) ||
-         (request.getType() == CacheRequestType_ST_XACT) ||
-         (request.getType() == CacheRequestType_LDX_XACT) ||
          (request.getType() == CacheRequestType_ATOMIC));
 
   hitCallback(request, data, respondingMach, thread);
@@ -549,7 +534,6 @@ void Sequencer::readCallback(const Address& address, DataBlock& data, GenericMac
   removeRequest(request);
 
   assert((request.getType() == CacheRequestType_LD) ||
-         (request.getType() == CacheRequestType_LD_XACT) ||
          (request.getType() == CacheRequestType_IFETCH)
          );
 
@@ -625,8 +609,6 @@ void Sequencer::hitCallback(const CacheMsg& request, DataBlock& data, GenericMac
 
   bool write =
     (type == CacheRequestType_ST) ||
-    (type == CacheRequestType_ST_XACT) ||
-    (type == CacheRequestType_LDX_XACT) ||
     (type == CacheRequestType_ATOMIC);
 
   if (TSO && write) {
@@ -654,130 +636,6 @@ void Sequencer::hitCallback(const CacheMsg& request, DataBlock& data, GenericMac
   }
 }
 
-void Sequencer::readConflictCallback(const Address& address) {
-  // process oldest thread first
-  int thread = -1;
-  Time oldest_time = 0;
-  int smt_threads = RubyConfig::numberofSMTThreads();
-  for(int t=0; t < smt_threads; ++t){
-    if(m_readRequestTable_ptr[t]->exist(address)){
-      CacheMsg & request = m_readRequestTable_ptr[t]->lookup(address);
-      if(thread == -1 || (request.getTime() < oldest_time) ){
-        thread = t;
-        oldest_time = request.getTime();
-      }
-    }
-  }
-  // make sure we found an oldest thread
-  ASSERT(thread != -1);
-
-  CacheMsg & request = m_readRequestTable_ptr[thread]->lookup(address);
-
-  readConflictCallback(address, GenericMachineType_NULL, thread);
-}
-
-void Sequencer::readConflictCallback(const Address& address, GenericMachineType respondingMach, int thread) {
-  assert(address == line_address(address));
-  assert(m_readRequestTable_ptr[thread]->exist(line_address(address)));
-
-  CacheMsg request = m_readRequestTable_ptr[thread]->lookup(address);
-  assert( request.getThreadID() == thread );
-  removeRequest(request);
-
-  assert((request.getType() == CacheRequestType_LD) ||
-         (request.getType() == CacheRequestType_LD_XACT) ||
-         (request.getType() == CacheRequestType_IFETCH)
-         );
-
-  conflictCallback(request, respondingMach, thread);
-}
-
-void Sequencer::writeConflictCallback(const Address& address) {
-  // process oldest thread first
-  int thread = -1;
-  Time oldest_time = 0;
-  int smt_threads = RubyConfig::numberofSMTThreads();
-  for(int t=0; t < smt_threads; ++t){
-    if(m_writeRequestTable_ptr[t]->exist(address)){
-      CacheMsg & request = m_writeRequestTable_ptr[t]->lookup(address);
-      if(thread == -1 || (request.getTime() < oldest_time) ){
-        thread = t;
-        oldest_time = request.getTime();
-      }
-    }
-  }
-  // make sure we found an oldest thread
-  ASSERT(thread != -1);
-
-  CacheMsg & request = m_writeRequestTable_ptr[thread]->lookup(address);
-
-  writeConflictCallback(address, GenericMachineType_NULL, thread);
-}
-
-void Sequencer::writeConflictCallback(const Address& address, GenericMachineType respondingMach, int thread) {
-  assert(address == line_address(address));
-  assert(m_writeRequestTable_ptr[thread]->exist(line_address(address)));
-  CacheMsg request = m_writeRequestTable_ptr[thread]->lookup(address);
-  assert( request.getThreadID() == thread);
-  removeRequest(request);
-
-  assert((request.getType() == CacheRequestType_ST) ||
-         (request.getType() == CacheRequestType_ST_XACT) ||
-         (request.getType() == CacheRequestType_LDX_XACT) ||
-         (request.getType() == CacheRequestType_ATOMIC));
-
-  conflictCallback(request, respondingMach, thread);
-
-}
-
-void Sequencer::conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread) {
-  assert(XACT_MEMORY);
-  int size = request.getSize();
-  Address request_address = request.getAddress();
-  Address request_logical_address = request.getLogicalAddress();
-  Address request_line_address = line_address(request_address);
-  CacheRequestType type = request.getType();
-  int threadID = request.getThreadID();
-  Time issued_time = request.getTime();
-  int logical_proc_no = ((m_chip_ptr->getID() * RubyConfig::numberOfProcsPerChip()) + m_version) * RubyConfig::numberofSMTThreads() + threadID;
-
-  DEBUG_MSG(SEQUENCER_COMP, MedPrio, size);
-
-  assert(g_eventQueue_ptr->getTime() >= issued_time);
-  Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
-
-  if (PROTOCOL_DEBUG_TRACE) {
-    g_system_ptr->getProfiler()->profileTransition("Seq", (m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version), -1, request.getAddress(), "", "Conflict", "",
-                                                   int_to_string(miss_latency)+" cycles "+GenericMachineType_to_string(respondingMach)+" "+CacheRequestType_to_string(request.getType())+" "+PrefetchBit_to_string(request.getPrefetch()));
-  }
-
-  DEBUG_MSG(SEQUENCER_COMP, MedPrio, request_address);
-  DEBUG_MSG(SEQUENCER_COMP, MedPrio, request.getPrefetch());
-  if (request.getPrefetch() == PrefetchBit_Yes) {
-    DEBUG_MSG(SEQUENCER_COMP, MedPrio, "return");
-    g_system_ptr->getProfiler()->swPrefetchLatency(miss_latency, type, respondingMach);
-    return; // Ignore the software prefetch, don't callback the driver
-  }
-
-  bool write =
-    (type == CacheRequestType_ST) ||
-    (type == CacheRequestType_ST_XACT) ||
-    (type == CacheRequestType_LDX_XACT) ||
-    (type == CacheRequestType_ATOMIC);
-
-  // Copy the correct bytes out of the cache line into the subblock
-  SubBlock subblock(request_address, request_logical_address, size);
-
-  // Call into the Driver (Tester or Simics)
-  g_system_ptr->getDriver()->conflictCallback(m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version, subblock, type, threadID);
-
-  // If the request was a Store or Atomic, apply the changes in the SubBlock to the DataBlock
-  // (This is only triggered for the non-TSO case)
-  if (write) {
-    assert(!TSO);
-  }
-}
-
 void Sequencer::printDebug(){
   //notify driver of debug
   g_system_ptr->getDriver()->printDebug();
@@ -814,9 +672,7 @@ Sequencer::isReady(const Packet* pkt) const
                    PrefetchBit_No,  // Not a prefetch
                    0,              // Version number
                    Address(logical_addr),   // Virtual Address
-                   thread,              // SMT thread
-                   0,          // TM specific - timestamp of memory request
-                   false      // TM specific - whether request is part of escape action
+                   thread              // SMT thread
                    );
   isReady(request);
 }
@@ -834,8 +690,6 @@ Sequencer::isReady(const CacheMsg& request) const
   // request outstanding for the line
   bool write =
     (request.getType() == CacheRequestType_ST) ||
-    (request.getType() == CacheRequestType_ST_XACT) ||
-    (request.getType() == CacheRequestType_LDX_XACT) ||
     (request.getType() == CacheRequestType_ATOMIC);
 
   // LUKE - disallow more than one request type per address
@@ -891,9 +745,7 @@ Sequencer::makeRequest(const Packet* pkt, void* data)
                    PrefetchBit_No, // Not a prefetch
                    0,              // Version number
                    Address(logical_addr),   // Virtual Address
-                   thread,         // SMT thread
-                   0,              // TM specific - timestamp of memory request
-                   false           // TM specific - whether request is part of escape action
+                   thread         // SMT thread
                    );
   makeRequest(request);
 }
@@ -902,8 +754,6 @@ void
 Sequencer::makeRequest(const CacheMsg& request)
 {
   bool write = (request.getType() == CacheRequestType_ST) ||
-    (request.getType() == CacheRequestType_ST_XACT) ||
-    (request.getType() == CacheRequestType_LDX_XACT) ||
     (request.getType() == CacheRequestType_ATOMIC);
 
   if (TSO && (request.getPrefetch() == PrefetchBit_No) && write) {
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index cd936a528..a3924b949 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -83,12 +83,6 @@ public:
   CacheMsg & getReadRequest( const Address & addr, int thread );
   CacheMsg & getWriteRequest( const Address & addr, int thread );
 
-  // called by Ruby when transaction completes
-  void writeConflictCallback(const Address& address);
-  void readConflictCallback(const Address& address);
-  void writeConflictCallback(const Address& address, GenericMachineType respondingMach, int thread);
-  void readConflictCallback(const Address& address, GenericMachineType respondingMach, int thread);
-
   void writeCallback(const Address& address, DataBlock& data);
   void readCallback(const Address& address, DataBlock& data);
   void writeCallback(const Address& address);
@@ -131,7 +125,7 @@ public:
 private:
   // Private Methods
   bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
-  void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread);
+  //  void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread);
   void hitCallback(const CacheMsg& request, DataBlock& data, GenericMachineType respondingMach, int thread);
   bool insertRequest(const CacheMsg& request);
 
diff --git a/src/mem/ruby/system/StoreBuffer.cc b/src/mem/ruby/system/StoreBuffer.cc
index 4dc54a481..7e5682fde 100644
--- a/src/mem/ruby/system/StoreBuffer.cc
+++ b/src/mem/ruby/system/StoreBuffer.cc
@@ -255,7 +255,7 @@ void StoreBuffer::processHeadOfQueue()
     assert(m_pending == false);
     m_pending = true;
     m_pending_address = entry.m_subblock.getAddress();
-    CacheMsg request(entry.m_subblock.getAddress(), entry.m_subblock.getAddress(), entry.m_type, entry.m_pc, entry.m_access_mode, entry.m_size, PrefetchBit_No, 0, Address(0), entry.m_thread, 0, false);
+    CacheMsg request(entry.m_subblock.getAddress(), entry.m_subblock.getAddress(), entry.m_type, entry.m_pc, entry.m_access_mode, entry.m_size, PrefetchBit_No, 0, Address(0), entry.m_thread);
     m_chip_ptr->getSequencer(m_version)->doRequest(request);
   }
 }
diff --git a/src/mem/ruby/tester/Check.cc b/src/mem/ruby/tester/Check.cc
index 3e2649709..0b278d110 100644
--- a/src/mem/ruby/tester/Check.cc
+++ b/src/mem/ruby/tester/Check.cc
@@ -85,7 +85,7 @@ void Check::initiatePrefetch(Sequencer* targetSequencer_ptr)
     type = CacheRequestType_ST;
   }
   assert(targetSequencer_ptr != NULL);
-  CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */, 0, false);
+  CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */);
   if (targetSequencer_ptr->isReady(request)) {
     targetSequencer_ptr->makeRequest(request);
   }
@@ -109,7 +109,7 @@ void Check::initiateAction()
     type = CacheRequestType_ATOMIC;
   }
 
-  CacheMsg request(Address(m_address.getAddress()+m_store_count), Address(m_address.getAddress()+m_store_count), type, m_pc, m_access_mode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false);
+  CacheMsg request(Address(m_address.getAddress()+m_store_count), Address(m_address.getAddress()+m_store_count), type, m_pc, m_access_mode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */);
   Sequencer* sequencer_ptr = initiatingSequencer();
   if (sequencer_ptr->isReady(request) == false) {
     DEBUG_MSG(TESTER_COMP, MedPrio, "failed to initiate action - sequencer not ready\n");
@@ -132,7 +132,7 @@ void Check::initiateCheck()
     type = CacheRequestType_IFETCH;
   }
 
-  CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, CHECK_SIZE, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false);
+  CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, CHECK_SIZE, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */);
   Sequencer* sequencer_ptr = initiatingSequencer();
   if (sequencer_ptr->isReady(request) == false) {
     DEBUG_MSG(TESTER_COMP, MedPrio, "failed to initiate check - sequencer not ready\n");
diff --git a/src/mem/ruby/tester/DetermGETXGenerator.cc b/src/mem/ruby/tester/DetermGETXGenerator.cc
index 1caebbdab..7e9c500c9 100644
--- a/src/mem/ruby/tester/DetermGETXGenerator.cc
+++ b/src/mem/ruby/tester/DetermGETXGenerator.cc
@@ -137,7 +137,7 @@ void DetermGETXGenerator::pickAddress()
 void DetermGETXGenerator::initiateStore()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
 }
 
 Sequencer* DetermGETXGenerator::sequencer() const
diff --git a/src/mem/ruby/tester/DetermInvGenerator.cc b/src/mem/ruby/tester/DetermInvGenerator.cc
index 020c2fe96..07c1a4b01 100644
--- a/src/mem/ruby/tester/DetermInvGenerator.cc
+++ b/src/mem/ruby/tester/DetermInvGenerator.cc
@@ -181,13 +181,13 @@ void DetermInvGenerator::pickLoadAddress()
 void DetermInvGenerator::initiateLoad()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Load");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
 }
 
 void DetermInvGenerator::initiateStore()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
 }
 
 Sequencer* DetermInvGenerator::sequencer() const
diff --git a/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc b/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
index 815919559..479b8b617 100644
--- a/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
+++ b/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
@@ -135,7 +135,7 @@ void DetermSeriesGETSGenerator::pickAddress()
 void DetermSeriesGETSGenerator::initiateLoad()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Load");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_IFETCH, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_IFETCH, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
 }
 
 Sequencer* DetermSeriesGETSGenerator::sequencer() const
diff --git a/src/mem/ruby/tester/RequestGenerator.cc b/src/mem/ruby/tester/RequestGenerator.cc
index 71a183315..b216e06fe 100644
--- a/src/mem/ruby/tester/RequestGenerator.cc
+++ b/src/mem/ruby/tester/RequestGenerator.cc
@@ -169,19 +169,19 @@ void RequestGenerator::pickAddress()
 void RequestGenerator::initiateTest()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Test");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
 }
 
 void RequestGenerator::initiateSwap()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Swap");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ATOMIC, Address(2), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ATOMIC, Address(2), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
 }
 
 void RequestGenerator::initiateRelease()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Release");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
 }
 
 Sequencer* RequestGenerator::sequencer() const