ruby: Removed g_SIMULATING flag

1. removed checks from tester files
2. removed else clause in Sequencer and DirectoryMemory else clause is
needed by the tester, it is up to Derek to revive it elsewhere when he
gets to it

Also:
1. Changed m_entries in DirectoryMemory to a map
2. And replaced SIMICS_read_physical_memory with a call to now-dummy
Derek's-to-be readPhysMem function

11 files changed, 35 insertions, 194 deletions

diff --git a/src/mem/ruby/config/config.hh b/src/mem/ruby/config/config.hh
index 3c3d87ef5..3cad258a2 100644
--- a/src/mem/ruby/config/config.hh
+++ b/src/mem/ruby/config/config.hh
@@ -134,7 +134,6 @@ PARAM_BOOL( REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH );
 // CACHE & MEMORY PARAMETERS
 // *********************************************
 
-PARAM_BOOL( g_SIMULATING );
 
 PARAM( L1_CACHE_ASSOC );
 PARAM( L1_CACHE_NUM_SETS_BITS );
diff --git a/src/mem/ruby/config/rubyconfig.defaults b/src/mem/ruby/config/rubyconfig.defaults
index 52b6603fb..873192c05 100644
--- a/src/mem/ruby/config/rubyconfig.defaults
+++ b/src/mem/ruby/config/rubyconfig.defaults
@@ -36,7 +36,6 @@
 //
 
 g_RANDOM_SEED: 1
-g_SIMULATING: true
 
 g_DEADLOCK_THRESHOLD: 500000
 
diff --git a/src/mem/ruby/config/tester.defaults b/src/mem/ruby/config/tester.defaults
index c9e963bda..6ba655770 100644
--- a/src/mem/ruby/config/tester.defaults
+++ b/src/mem/ruby/config/tester.defaults
@@ -6,7 +6,6 @@
 // Please: - Add new variables only to rubyconfig.defaults file.
 //         - Change them here only when necessary.
 
-g_SIMULATING: false
 DATA_BLOCK: true
 RANDOMIZATION: true
 g_SYNTHETIC_DRIVER: true
diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc
index d4c85cbea..a5f1bcddc 100644
--- a/src/mem/ruby/system/DirectoryMemory.cc
+++ b/src/mem/ruby/system/DirectoryMemory.cc
@@ -51,6 +51,7 @@ DirectoryMemory::DirectoryMemory(Chip* chip_ptr, int version)
   // m_size = RubyConfig::memoryModuleBlocks()/RubyConfig::numberOfDirectory();
   m_size = RubyConfig::memoryModuleBlocks();
   assert(m_size > 0);
+  /*********************************************************************
   // allocates an array of directory entry pointers & sets them to NULL
   m_entries = new Directory_Entry*[m_size];
   if (m_entries == NULL) {
@@ -60,10 +61,12 @@ DirectoryMemory::DirectoryMemory(Chip* chip_ptr, int version)
   for (int i=0; i < m_size; i++) {
     m_entries[i] = NULL;
   }
+  */////////////////////////////////////////////////////////////////////
 }
 
 DirectoryMemory::~DirectoryMemory()
 {
+  /*********************************************************************
   // free up all the directory entries
   for (int i=0; i < m_size; i++) {
     if (m_entries[i] != NULL) {
@@ -74,6 +77,8 @@ DirectoryMemory::~DirectoryMemory()
 
   // free up the array of directory entries
   delete[] m_entries;
+  *//////////////////////////////////////////////////////////////////////
+  m_entries.clear();
 }
 
 // Static method
@@ -99,6 +104,10 @@ bool DirectoryMemory::isPresent(PhysAddress address)
   return (map_Address_to_DirectoryNode(address) == m_chip_ptr->getID()*RubyConfig::numberOfDirectoryPerChip()+m_version);
 }
 
+void DirectoryMemory::readPhysMem(uint64 address, int size, void * data)
+{
+}
+
 Directory_Entry& DirectoryMemory::lookup(PhysAddress address)
 {
   assert(isPresent(address));
@@ -111,35 +120,29 @@ Directory_Entry& DirectoryMemory::lookup(PhysAddress address)
     WARN_EXPR(m_size);
     ERROR_MSG("Directory Memory Assertion: accessing memory out of range.");
   }
-  Directory_Entry* entry = m_entries[index];
+
+  map<Index, Directory_Entry*>::iterator iter =  m_entries.find(index);
+  Directory_Entry* entry = m_entries.find(index)->second;
 
   // allocate the directory entry on demand.
-  if (entry == NULL) {
+  if (iter == m_entries.end()) {
     entry = new Directory_Entry;
 
     //    entry->getProcOwner() = m_chip_ptr->getID(); // FIXME - This should not be hard coded
     //    entry->getDirOwner() = true;        // FIXME - This should not be hard-coded
 
-    // load the data from SimICS when first initalizing
-    if (g_SIMULATING) {
-      if (DATA_BLOCK) {
-        //physical_address_t physAddr = address.getAddress();
-
-        for(int j=0; j < RubyConfig::dataBlockBytes(); j++) {
-          //int8 data_byte = (int8) SIMICS_read_physical_memory( m_chip_ptr->getID(),
-          //                                                     physAddr + j, 1 );
-          //printf("SimICS, byte %d: %lld\n", j, data_byte );
-          int8 data_byte = 0;
-          entry->getDataBlk().setByte(j, data_byte);
-        }
-        DEBUG_EXPR(NODE_COMP, MedPrio,entry->getDataBlk());
-      }
-    }
+    // load the data from physicalMemory when first initalizing
+    physical_address_t physAddr = address.getAddress();
+    int8 * dataArray = (int8 * )malloc(RubyConfig::dataBlockBytes() * sizeof(int8));
+    readPhysMem(physAddr, RubyConfig::dataBlockBytes(), dataArray);
 
+    for(int j=0; j < RubyConfig::dataBlockBytes(); j++) {
+      entry->getDataBlk().setByte(j, dataArray[j]);
+    }
+    DEBUG_EXPR(NODE_COMP, MedPrio,entry->getDataBlk());
     // store entry to the table
-    m_entries[index] = entry;
+    m_entries.insert(make_pair(index, entry));
   }
-
   return (*entry);
 }
 
@@ -165,11 +168,9 @@ void DirectoryMemory::invalidateBlock(PhysAddress address)
 void DirectoryMemory::print(ostream& out) const
 {
   out << "Directory dump: " << endl;
-  for (int i=0; i < m_size; i++) {
-    if (m_entries[i] != NULL) {
-      out << i << ": ";
-      out << *m_entries[i] << endl;
-    }
+  for(map<Index, Directory_Entry*>::const_iterator it = m_entries.begin(); it != m_entries.end(); ++it) {
+      out << it->first << ": ";
+      out << *(it->second) << endl;
   }
 }
 
diff --git a/src/mem/ruby/system/DirectoryMemory.hh b/src/mem/ruby/system/DirectoryMemory.hh
index 94b7de9aa..3307e77a7 100644
--- a/src/mem/ruby/system/DirectoryMemory.hh
+++ b/src/mem/ruby/system/DirectoryMemory.hh
@@ -42,6 +42,7 @@
 #include "mem/ruby/common/Global.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/protocol/Directory_Entry.hh"
+#include <map>
 
 class Chip;
 
@@ -56,6 +57,8 @@ public:
   // Public Methods
   static void printConfig(ostream& out);
   bool isPresent(PhysAddress address);
+  // dummy function
+  void readPhysMem(uint64 address, int size, void * data);
   Directory_Entry& lookup(PhysAddress address);
 
   void print(ostream& out) const;
@@ -68,7 +71,7 @@ private:
   DirectoryMemory& operator=(const DirectoryMemory& obj);
 
   // Data Members (m_ prefix)
-  Directory_Entry **m_entries;
+  map<Index, Directory_Entry*> m_entries;
   Chip* m_chip_ptr;
   int m_size;  // # of memory module blocks for this directory
   int m_version;
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 0950741dc..87fbc66b5 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -939,157 +939,18 @@ void Sequencer::checkCoherence(const Address& addr) {
 
 bool Sequencer::getRubyMemoryValue(const Address& addr, char* value,
                                    unsigned int size_in_bytes ) {
-  if(g_SIMULATING){
-    for(unsigned int i=0; i < size_in_bytes; i++) {
-      std::cerr << __FILE__ << "(" << __LINE__ << "): Not implemented. " << std::endl;
-      value[i] = 0; // _read_physical_memory( m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version,
-                    //                          addr.getAddress() + i, 1 );
-    }
-    return false; // Do nothing?
-  } else {
-    bool found = false;
-    const Address lineAddr = line_address(addr);
-    DataBlock data;
-    PhysAddress paddr(addr);
-    DataBlock* dataPtr = &data;
-    Chip* n = dynamic_cast<Chip*>(m_chip_ptr);
-    // LUKE - use variable names instead of macros
-    assert(n->m_L1Cache_L1IcacheMemory_vec[m_version] != NULL);
-    assert(n->m_L1Cache_L1DcacheMemory_vec[m_version] != NULL);
-
-    MachineID l2_mach = map_L2ChipId_to_L2Cache(addr, m_chip_ptr->getID() );
-    int l2_ver = l2_mach.num%RubyConfig::numberOfL2CachePerChip();
-
-    if (Protocol::m_TwoLevelCache) {
-      if(Protocol::m_CMP){
-        assert(n->m_L2Cache_L2cacheMemory_vec[l2_ver] != NULL);
-      }
-      else{
-        assert(n->m_L1Cache_cacheMemory_vec[m_version] != NULL);
-      }
-    }
-
-    if (n->m_L1Cache_L1IcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_IFETCH, dataPtr)){
-      n->m_L1Cache_L1IcacheMemory_vec[m_version]->getMemoryValue(addr, value, size_in_bytes);
-      found = true;
-    } else if (n->m_L1Cache_L1DcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){
-      n->m_L1Cache_L1DcacheMemory_vec[m_version]->getMemoryValue(addr, value, size_in_bytes);
-      found = true;
-    } else if (Protocol::m_CMP && n->m_L2Cache_L2cacheMemory_vec[l2_ver]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){
-      n->m_L2Cache_L2cacheMemory_vec[l2_ver]->getMemoryValue(addr, value, size_in_bytes);
-      found = true;
-      // } else if (n->TBE_TABLE_MEMBER_VARIABLE->isPresent(lineAddr)){
-      //       ASSERT(n->TBE_TABLE_MEMBER_VARIABLE->isPresent(lineAddr));
-      //       L1Cache_TBE tbeEntry = n->TBE_TABLE_MEMBER_VARIABLE->lookup(lineAddr);
-
-      //       int offset = addr.getOffset();
-      //       for(int i=0; i<size_in_bytes; ++i){
-      //         value[i] = tbeEntry.getDataBlk().getByte(offset + i);
-      //       }
-
-      //       found = true;
-    } else {
-      // Address not found
-      //cout << "  " << m_chip_ptr->getID() << " NOT IN CACHE, Value at Directory is: " << (int) value[0] << endl;
-      n = dynamic_cast<Chip*>(g_system_ptr->getChip(map_Address_to_DirectoryNode(addr)/RubyConfig::numberOfDirectoryPerChip()));
-      int dir_version = map_Address_to_DirectoryNode(addr)%RubyConfig::numberOfDirectoryPerChip();
-      for(unsigned int i=0; i<size_in_bytes; ++i){
-        int offset = addr.getOffset();
-        value[i] = n->m_Directory_directory_vec[dir_version]->lookup(lineAddr).m_DataBlk.getByte(offset + i);
-      }
-      // Address not found
-      //WARN_MSG("Couldn't find address");
-      //WARN_EXPR(addr);
-      found = false;
-    }
-    return true;
+  for(unsigned int i=0; i < size_in_bytes; i++) {
+    std::cerr << __FILE__ << "(" << __LINE__ << "): Not implemented. " << std::endl;
+    value[i] = 0; // _read_physical_memory( m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version,
+                  //                          addr.getAddress() + i, 1 );
   }
+  return false; // Do nothing?
 }
 
 bool Sequencer::setRubyMemoryValue(const Address& addr, char *value,
                                    unsigned int size_in_bytes) {
   char test_buffer[64];
 
-  if(g_SIMULATING){
-    return false; // Do nothing?
-  } else {
-    // idea here is that coherent cache should find the
-    // latest data, the update it
-    bool found = false;
-    const Address lineAddr = line_address(addr);
-    PhysAddress paddr(addr);
-    DataBlock data;
-    DataBlock* dataPtr = &data;
-    Chip* n = dynamic_cast<Chip*>(m_chip_ptr);
-
-    MachineID l2_mach = map_L2ChipId_to_L2Cache(addr, m_chip_ptr->getID() );
-    int l2_ver = l2_mach.num%RubyConfig::numberOfL2CachePerChip();
-    // LUKE - use variable names instead of macros
-    //cout << "number of L2caches per chip = " << RubyConfig::numberOfL2CachePerChip(m_version) << endl;
-    //cout << "L1I cache vec size = " << n->m_L1Cache_L1IcacheMemory_vec.size() << endl;
-    //cout << "L1D cache vec size = " << n->m_L1Cache_L1DcacheMemory_vec.size() << endl;
-    //cout << "L1cache_cachememory size = " << n->m_L1Cache_cacheMemory_vec.size() << endl;
-    //cout << "L1cache_l2cachememory size = " << n->m_L1Cache_L2cacheMemory_vec.size() << endl;
-    // if (Protocol::m_TwoLevelCache) {
-    //       if(Protocol::m_CMP){
-    //         cout << "CMP L2 cache vec size = " << n->m_L2Cache_L2cacheMemory_vec.size() << endl;
-    //       }
-    //       else{
-    //        cout << "L2 cache vec size = " << n->m_L1Cache_cacheMemory_vec.size() << endl;
-    //       }
-    //     }
-
-    assert(n->m_L1Cache_L1IcacheMemory_vec[m_version] != NULL);
-    assert(n->m_L1Cache_L1DcacheMemory_vec[m_version] != NULL);
-    if (Protocol::m_TwoLevelCache) {
-      if(Protocol::m_CMP){
-        assert(n->m_L2Cache_L2cacheMemory_vec[l2_ver] != NULL);
-      }
-      else{
-        assert(n->m_L1Cache_cacheMemory_vec[m_version] != NULL);
-      }
-    }
-
-    if (n->m_L1Cache_L1IcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_IFETCH, dataPtr)){
-      n->m_L1Cache_L1IcacheMemory_vec[m_version]->setMemoryValue(addr, value, size_in_bytes);
-      found = true;
-    } else if (n->m_L1Cache_L1DcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){
-      n->m_L1Cache_L1DcacheMemory_vec[m_version]->setMemoryValue(addr, value, size_in_bytes);
-      found = true;
-    } else if (Protocol::m_CMP && n->m_L2Cache_L2cacheMemory_vec[l2_ver]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){
-      n->m_L2Cache_L2cacheMemory_vec[l2_ver]->setMemoryValue(addr, value, size_in_bytes);
-      found = true;
-      // } else if (n->TBE_TABLE_MEMBER_VARIABLE->isTagPresent(lineAddr)){
-      //       L1Cache_TBE& tbeEntry = n->TBE_TABLE_MEMBER_VARIABLE->lookup(lineAddr);
-      //       DataBlock tmpData;
-      //       int offset = addr.getOffset();
-      //       for(int i=0; i<size_in_bytes; ++i){
-      //         tmpData.setByte(offset + i, value[i]);
-      //       }
-      //       tbeEntry.setDataBlk(tmpData);
-      //       tbeEntry.setDirty(true);
-    } else {
-      // Address not found
-      n = dynamic_cast<Chip*>(g_system_ptr->getChip(map_Address_to_DirectoryNode(addr)/RubyConfig::numberOfDirectoryPerChip()));
-      int dir_version = map_Address_to_DirectoryNode(addr)%RubyConfig::numberOfDirectoryPerChip();
-      for(unsigned int i=0; i<size_in_bytes; ++i){
-        int offset = addr.getOffset();
-        n->m_Directory_directory_vec[dir_version]->lookup(lineAddr).m_DataBlk.setByte(offset + i, value[i]);
-      }
-      found = false;
-    }
-
-    if (found){
-      found = getRubyMemoryValue(addr, test_buffer, size_in_bytes);
-      assert(found);
-      if(value[0] != test_buffer[0]){
-        WARN_EXPR((int) value[0]);
-        WARN_EXPR((int) test_buffer[0]);
-        ERROR_MSG("setRubyMemoryValue failed to set value.");
-      }
-    }
-
-    return true;
-  }
+  return false; // Do nothing?
 }
 
diff --git a/src/mem/ruby/tester/DeterministicDriver.cc b/src/mem/ruby/tester/DeterministicDriver.cc
index bc27c2a35..7b7d0c9d2 100644
--- a/src/mem/ruby/tester/DeterministicDriver.cc
+++ b/src/mem/ruby/tester/DeterministicDriver.cc
@@ -45,10 +45,6 @@
 
 DeterministicDriver::DeterministicDriver(RubySystem* sys_ptr)
 {
-  if (g_SIMULATING) {
-    ERROR_MSG("g_SIMULATING should not be defined.");
-  }
-
   m_finish_time = 0;
   m_last_issue = -11;
   m_done_counter = 0;
diff --git a/src/mem/ruby/tester/RaceyDriver.cc b/src/mem/ruby/tester/RaceyDriver.cc
index 6ea9ec795..c56557645 100644
--- a/src/mem/ruby/tester/RaceyDriver.cc
+++ b/src/mem/ruby/tester/RaceyDriver.cc
@@ -41,10 +41,6 @@
 
 RaceyDriver::RaceyDriver()
 {
-  if (g_SIMULATING) {
-    ERROR_MSG("g_SIMULATING should not be defined.");
-  }
-
   // debug transition?
   if(false) {
     assert(g_debug_ptr);
diff --git a/src/mem/ruby/tester/SyntheticDriver.cc b/src/mem/ruby/tester/SyntheticDriver.cc
index 1d8dcb80a..081fc9d5e 100644
--- a/src/mem/ruby/tester/SyntheticDriver.cc
+++ b/src/mem/ruby/tester/SyntheticDriver.cc
@@ -42,11 +42,6 @@
 
 SyntheticDriver::SyntheticDriver(RubySystem* sys_ptr)
 {
-  cout << "SyntheticDriver::SyntheticDriver" << endl;
-  if (g_SIMULATING) {
-    ERROR_MSG("g_SIMULATING should not be defined.");
-  }
-
   m_finish_time = 0;
   m_done_counter = 0;
 
diff --git a/src/mem/ruby/tester/Tester.cc b/src/mem/ruby/tester/Tester.cc
index 53d6bc670..eafc04a92 100644
--- a/src/mem/ruby/tester/Tester.cc
+++ b/src/mem/ruby/tester/Tester.cc
@@ -42,10 +42,6 @@
 
 Tester::Tester(RubySystem* sys_ptr)
 {
-  if (g_SIMULATING) {
-    ERROR_MSG("g_SIMULATING should not be defined.");
-  }
-
   g_callback_counter = 0;
 
   // add the tester consumer to the global event queue
diff --git a/src/mem/ruby/tester/main.cc b/src/mem/ruby/tester/main.cc
index f36168c8e..5e77488e9 100644
--- a/src/mem/ruby/tester/main.cc
+++ b/src/mem/ruby/tester/main.cc
@@ -43,9 +43,5 @@
 
 int main(int argc, char *argv[])
 {
-  if (g_SIMULATING) {
-    ERROR_MSG("g_SIMULATING should not be defined.");
-  }
-
   tester_main(argc, argv);
 }