ruby: tag and data cache access support

Updates to Ruby to support statistics counting of cache accesses.  This feature
serves multiple purposes beyond simple stats collection.  It provides the
foundation for ruby to model the cache tag and data arrays as physical
resources, as well as provide the necessary input data for McPAT power
modeling.

10 files changed, 99 insertions, 0 deletions

diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index 9144a8dff..a626dc13f 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -29,6 +29,7 @@
 #include "base/intmath.hh"
 #include "debug/RubyCache.hh"
 #include "debug/RubyCacheTrace.hh"
+#include "debug/RubyStats.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/system/CacheMemory.hh"
 #include "mem/ruby/system/System.hh"
@@ -476,3 +477,50 @@ CacheMemory::isLocked(const Address& address, int context)
     return m_cache[cacheSet][loc]->m_locked == context;
 }
 
+void
+CacheMemory::recordRequestType(CacheRequestType requestType) {
+    DPRINTF(RubyStats, "Recorded statistic: %s\n",
+            CacheRequestType_to_string(requestType));
+    switch(requestType) {
+    case CacheRequestType_DataArrayRead:
+        numDataArrayReads++;
+        return;
+    case CacheRequestType_DataArrayWrite:
+        numDataArrayWrites++;
+        return;
+    case CacheRequestType_TagArrayRead:
+        numTagArrayReads++;
+        return;
+    case CacheRequestType_TagArrayWrite:
+        numTagArrayWrites++;
+        return;
+    default:
+        warn("CacheMemory access_type not found: %s",
+             CacheRequestType_to_string(requestType));
+    }
+}
+
+void
+CacheMemory::regStats() {
+    using namespace Stats;
+
+    numDataArrayReads
+        .name(name() + ".num_data_array_reads")
+        .desc("number of data array reads")
+        ;
+
+    numDataArrayWrites
+        .name(name() + ".num_data_array_writes")
+        .desc("number of data array writes")
+        ;
+
+    numTagArrayReads
+        .name(name() + ".num_tag_array_reads")
+        .desc("number of tag array reads")
+        ;
+
+    numTagArrayWrites
+        .name(name() + ".num_tag_array_writes")
+        .desc("number of tag array writes")
+        ;
+}
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index f270e88cd..53cd6b286 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -34,6 +34,8 @@
 #include <vector>
 
 #include "base/hashmap.hh"
+#include "base/statistics.hh"
+#include "mem/protocol/CacheRequestType.hh"
 #include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/common/DataBlock.hh"
@@ -115,6 +117,14 @@ class CacheMemory : public SimObject
     void clearStats() const;
     void printStats(std::ostream& out) const;
 
+    void recordRequestType(CacheRequestType requestType);
+    void regStats();
+
+    Stats::Scalar numDataArrayReads;
+    Stats::Scalar numDataArrayWrites;
+    Stats::Scalar numTagArrayReads;
+    Stats::Scalar numTagArrayWrites;
+
   private:
     // convert a Address to its location in the cache
     Index addressToCacheSet(const Address& address) const;
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 763eb586a..b1502573b 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -27,6 +27,7 @@
  */
 
 #include "debug/RubyDma.hh"
+#include "debug/RubyStats.hh"
 #include "mem/protocol/SequencerMsg.hh"
 #include "mem/protocol/SequencerRequestType.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
@@ -168,6 +169,12 @@ DMASequencer::printConfig(std::ostream & out)
 {
 }
 
+void
+DMASequencer::recordRequestType(DMASequencerRequestType requestType) {
+    DPRINTF(RubyStats, "Recorded statistic: %s\n",
+            DMASequencerRequestType_to_string(requestType));
+}
+
 DMASequencer *
 DMASequencerParams::create()
 {
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 099c1d991..d1fb2ff49 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -31,6 +31,7 @@
 
 #include <ostream>
 
+#include "mem/protocol/DMASequencerRequestType.hh"
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/system/RubyPort.hh"
 #include "params/DMASequencer.hh"
@@ -65,6 +66,8 @@ class DMASequencer : public RubyPort
 
     void printConfig(std::ostream & out);
 
+    void recordRequestType(DMASequencerRequestType requestType);
+
   private:
     void issueNext();
 
diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc
index d2e00ab3b..c67babda4 100644
--- a/src/mem/ruby/system/DirectoryMemory.cc
+++ b/src/mem/ruby/system/DirectoryMemory.cc
@@ -28,6 +28,7 @@
 
 #include "base/intmath.hh"
 #include "debug/RubyCache.hh"
+#include "debug/RubyStats.hh"
 #include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
 #include "mem/ruby/system/DirectoryMemory.hh"
 #include "mem/ruby/system/System.hh"
@@ -226,6 +227,12 @@ DirectoryMemory::printStats(ostream& out) const
     }
 }
 
+void
+DirectoryMemory::recordRequestType(DirectoryRequestType requestType) {
+    DPRINTF(RubyStats, "Recorded statistic: %s\n",
+            DirectoryRequestType_to_string(requestType));
+}
+
 DirectoryMemory *
 RubyDirectoryMemoryParams::create()
 {
diff --git a/src/mem/ruby/system/DirectoryMemory.hh b/src/mem/ruby/system/DirectoryMemory.hh
index 1b4d09b8e..61938f7c8 100644
--- a/src/mem/ruby/system/DirectoryMemory.hh
+++ b/src/mem/ruby/system/DirectoryMemory.hh
@@ -33,6 +33,7 @@
 #include <string>
 
 #include "mem/ruby/common/Address.hh"
+#include "mem/protocol/DirectoryRequestType.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
 #include "mem/ruby/system/MemoryVector.hh"
 #include "mem/ruby/system/SparseMemory.hh"
@@ -66,6 +67,8 @@ class DirectoryMemory : public SimObject
     void print(std::ostream& out) const;
     void printStats(std::ostream& out) const;
 
+    void recordRequestType(DirectoryRequestType requestType);
+
   private:
     // Private copy constructor and assignment operator
     DirectoryMemory(const DirectoryMemory& obj);
diff --git a/src/mem/ruby/system/MemoryControl.cc b/src/mem/ruby/system/MemoryControl.cc
index c3b34d965..14a34be4a 100644
--- a/src/mem/ruby/system/MemoryControl.cc
+++ b/src/mem/ruby/system/MemoryControl.cc
@@ -29,6 +29,7 @@
 
 #include "base/cast.hh"
 #include "base/cprintf.hh"
+#include "debug/RubyStats.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/common/Global.hh"
@@ -48,6 +49,12 @@ MemoryControl::MemoryControl(const Params *p) : SimObject(p), m_event(this)
 
 MemoryControl::~MemoryControl() {};
 
+void
+MemoryControl::recordRequestType(MemoryControlRequestType request) {
+    DPRINTF(RubyStats, "Recorded request: %s\n",
+            MemoryControlRequestType_to_string(request));
+}
+
 RubyMemoryControl *
 RubyMemoryControlParams::create()
 {
diff --git a/src/mem/ruby/system/MemoryControl.hh b/src/mem/ruby/system/MemoryControl.hh
index 7e35ef7a0..6a3ca48d9 100644
--- a/src/mem/ruby/system/MemoryControl.hh
+++ b/src/mem/ruby/system/MemoryControl.hh
@@ -35,6 +35,7 @@
 #include <string>
 
 #include "mem/protocol/MemoryMsg.hh"
+#include "mem/protocol/MemoryControlRequestType.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/profiler/MemCntrlProfiler.hh"
 #include "mem/ruby/slicc_interface/Message.hh"
@@ -95,6 +96,8 @@ class MemoryControl :
     virtual int getRanksPerDimm() = 0;
     virtual int getDimmsPerChannel() = 0;
 
+    virtual void recordRequestType(MemoryControlRequestType requestType);
+
 protected:
     class MemCntrlEvent : public Event
     {
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index de7c8154b..8733ec514 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -36,6 +36,7 @@
 #include "debug/MemoryAccess.hh"
 #include "debug/ProtocolTrace.hh"
 #include "debug/RubySequencer.hh"
+#include "debug/RubyStats.hh"
 #include "mem/protocol/PrefetchBit.hh"
 #include "mem/protocol/RubyAccessMode.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
@@ -731,6 +732,13 @@ Sequencer::checkCoherence(const Address& addr)
 }
 
 void
+Sequencer::recordRequestType(SequencerRequestType requestType) {
+    DPRINTF(RubyStats, "Recorded statistic: %s\n",
+            SequencerRequestType_to_string(requestType));
+}
+
+
+void
 Sequencer::evictionCallback(const Address& address)
 {
     ruby_eviction_callback(address);
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 296258994..2778cf380 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -34,6 +34,7 @@
 #include "base/hashmap.hh"
 #include "mem/protocol/GenericMachineType.hh"
 #include "mem/protocol/RubyRequestType.hh"
+#include "mem/protocol/SequencerRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/system/RubyPort.hh"
@@ -119,6 +120,8 @@ class Sequencer : public RubyPort, public Consumer
     void removeRequest(SequencerRequest* request);
     void evictionCallback(const Address& address);
 
+    void recordRequestType(SequencerRequestType requestType);
+
   private:
     void issueRequest(PacketPtr pkt, RubyRequestType type);