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authorDibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <gope@wisc.edu>2013-02-28 10:04:26 -0600
committerDibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <gope@wisc.edu>2013-02-28 10:04:26 -0600
commitc636a09e83b08c27ce60a0f1d13536d736a06926 (patch)
tree06f6c03aa546d90b18752f218b52d84c6f1eb96e /src/mem/ruby
parent82cf1565d02608111459379634c6daa31d4a6895 (diff)
downloadgem5-c636a09e83b08c27ce60a0f1d13536d736a06926.tar.xz
ruby: mesi coherence protocol: invalidate lock
The MESI CMP directory coherence protocol, while transitioning from SM to IM, did not invalidate the lock that it might have taken on a cache line. This patch adds an action for doing so. The problem was found by Dibakar, but I was not happy with his proposed solution. So I implemented a different solution. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem/ruby')
-rw-r--r--src/mem/ruby/system/Sequencer.cc15
-rw-r--r--src/mem/ruby/system/Sequencer.hh1
2 files changed, 15 insertions, 1 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index f00f8407a..54fb83dd0 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -306,6 +306,20 @@ Sequencer::removeRequest(SequencerRequest* srequest)
markRemoved();
}
+void
+Sequencer::invalidateSC(const Address& address)
+{
+ RequestTable::iterator i = m_writeRequestTable.find(address);
+ if (i != m_writeRequestTable.end()) {
+ SequencerRequest* request = i->second;
+ // The controller has lost the coherence permissions, hence the lock
+ // on the cache line maintained by the cache should be cleared.
+ if (request->m_type == RubyRequestType_Store_Conditional) {
+ m_dataCache_ptr->clearLocked(address);
+ }
+ }
+}
+
bool
Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
{
@@ -392,7 +406,6 @@ Sequencer::writeCallback(const Address& address,
(request->m_type == RubyRequestType_Locked_RMW_Write) ||
(request->m_type == RubyRequestType_FLUSH));
-
//
// For Alpha, properly handle LL, SC, and write requests with respect to
// locked cache blocks.
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index b3ec4d10a..782b776f9 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -116,6 +116,7 @@ class Sequencer : public RubyPort
void markRemoved();
void removeRequest(SequencerRequest* request);
void evictionCallback(const Address& address);
+ void invalidateSC(const Address& address);
void recordRequestType(SequencerRequestType requestType);