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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-04-06 13:47:06 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-04-06 13:47:06 -0700 |
| commit | 0a9f4b950fb52db3951ad1f7aafc674b505d2679 (patch) | |
| tree | 033bfd48877875c00201058f1a60e679696c9cdf /src/mem/ruby | |
| parent | b00949d88bb3185dfa2e27799de7f90e5a449be8 (diff) | |
| download | gem5-0a9f4b950fb52db3951ad1f7aafc674b505d2679.tar.xz | |
rubytest: seperated read and write ports.
This patch allows the ruby tester to support protocols where the i-cache and d-cache
are managed by seperate controllers.
Diffstat (limited to 'src/mem/ruby')
| -rw-r--r-- | src/mem/ruby/system/Sequencer.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 02686d33f..79cf9709e 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -44,6 +44,9 @@ class RubyPort(MemObject): "should the rubyport atomically update phys_mem") ruby_system = Param.RubySystem("") system = Param.System(Parent.any, "system object") + support_data_reqs = Param.Bool(True, "data cache requests supported") + support_inst_reqs = Param.Bool(True, "inst cache requests supported") + class RubyPortProxy(RubyPort): type = 'RubyPortProxy' |