ruby: change router pipeline stages to 2

This patch changes the router pipeline stages from 4 to 2. The
canonical 4-stage router is conservative while a lower-latency router
with look ahead routing and speculative allocation is well acknowledged.

10 files changed, 36 insertions, 15 deletions

diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
index fb147babc..2f99d387a 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
@@ -81,8 +81,14 @@ InputUnit_d::wakeup()
 
             m_vcs[vc]->set_enqueue_time(m_router->curCycle());
         } else {
-            t_flit->advance_stage(SA_, m_router->curCycle() + Cycles(1));
-            m_router->swarb_req();
+            t_flit->advance_stage(SA_, m_router->curCycle());
+            // Changing router latency to 2 cycles. Input Unit takes 1 cycle for wakeup.
+            // VCalloc, SWalloc, Sw-Xfer and output scheduling takes 1 cycle. The original
+            // design schedules VCallocator for head flit, and Swalloc for non-head flit.
+            // VCalloc now calls SWalloc directly instead of scheduling it for the next cycle,
+            // hence we should not allocate SWalloc, otherwise it might get called twice, once
+            // by the scheduler and once by VCalloc.
+            m_router->vcarb_req();
         }
         // write flit into input buffer
         m_vcs[vc]->insertFlit(t_flit);
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
index f090e2a63..9ef2ca271 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
@@ -102,7 +102,7 @@ OutputUnit_d::set_credit_link(CreditLink_d *credit_link)
 void
 OutputUnit_d::update_vc(int vc, int in_port, int in_vc)
 {
-    m_outvc_state[vc]->setState(ACTIVE_, m_router->curCycle() + Cycles(1));
+  m_outvc_state[vc]->setState(ACTIVE_, m_router->curCycle());
     m_outvc_state[vc]->set_inport(in_port);
     m_outvc_state[vc]->set_invc(in_vc);
     m_router->update_incredit(in_port, in_vc,
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
index f0b0fc64f..85b0f6a38 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
@@ -70,7 +70,7 @@ class OutputUnit_d : public Consumer
     inline void
     set_vc_state(VC_state_type state, int vc, Cycles curTime)
     {
-        m_outvc_state[vc]->setState(state, curTime + Cycles(1));
+      m_outvc_state[vc]->setState(state, curTime);
     }
 
     inline bool
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
index 126cf79e6..97bc1abdd 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
@@ -131,6 +131,18 @@ Router_d::swarb_req()
 }
 
 void
+Router_d::call_sw_alloc()
+{
+    m_sw_alloc->wakeup();
+}
+
+void
+Router_d::call_switch()
+{
+    m_switch->wakeup();
+}
+
+void
 Router_d::update_incredit(int in_port, int in_vc, int credit)
 {
     m_input_unit[in_port]->update_credit(in_vc, credit);
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
index 5d09fb045..9b384596e 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
@@ -85,6 +85,8 @@ class Router_d : public BasicRouter
     void route_req(flit_d *t_flit, InputUnit_d* in_unit, int invc);
     void vcarb_req();
     void swarb_req();
+    void call_sw_alloc();
+    void call_switch();
 
     void printFaultVector(std::ostream& out);
     void printAggregateFaultProbability(std::ostream& out);
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
index 21fbfe6e5..1e636b589 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
@@ -82,6 +82,7 @@ SWallocator_d::wakeup()
 
     clear_request_vector();
     check_for_wakeup();
+    m_router->call_switch();
 
 }
 
@@ -178,10 +179,10 @@ SWallocator_d::arbitrate_outports()
 
                 // remove flit from Input Unit
                 flit_d *t_flit = m_input_unit[inport]->getTopFlit(invc);
-                t_flit->advance_stage(ST_, m_router->curCycle() + Cycles(1));
+                t_flit->advance_stage(ST_, m_router->curCycle());
                 t_flit->set_vc(outvc);
                 t_flit->set_outport(outport);
-                t_flit->set_time(m_router->curCycle() + Cycles(1));
+                t_flit->set_time(m_router->curCycle());
 
                 m_output_unit[outport]->decrement_credit(outvc);
                 m_router->update_sw_winner(inport, t_flit);
@@ -223,7 +224,7 @@ SWallocator_d::check_for_wakeup()
     for (int i = 0; i < m_num_inports; i++) {
         for (int j = 0; j < m_num_vcs; j++) {
             if (m_input_unit[i]->need_stage(j, ACTIVE_, SA_, nextCycle)) {
-                scheduleEvent(Cycles(1));
+                m_router->vcarb_req();
                 return;
             }
         }
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
index 911c5a6eb..25dc26e51 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
@@ -73,8 +73,8 @@ Switch_d::wakeup()
         flit_d *t_flit = m_switch_buffer[inport]->peekTopFlit();
         if (t_flit->is_stage(ST_, m_router->curCycle())) {
             int outport = t_flit->get_outport();
-            t_flit->advance_stage(LT_, m_router->curCycle() + Cycles(1));
-            t_flit->set_time(m_router->curCycle() + Cycles(1));
+            t_flit->advance_stage(LT_, m_router->curCycle());
+            t_flit->set_time(m_router->curCycle());
 
             // This will take care of waking up the Network Link
             m_output_unit[outport]->insert_flit(t_flit);
@@ -92,7 +92,7 @@ Switch_d::check_for_wakeup()
 
     for (int inport = 0; inport < m_num_inports; inport++) {
         if (m_switch_buffer[inport]->isReady(nextCycle)) {
-            scheduleEvent(Cycles(1));
+            m_router->vcarb_req();
             break;
         }
     }
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
index 395b1a9c5..a7430b06e 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
@@ -117,6 +117,7 @@ VCallocator_d::wakeup()
 
     clear_request_vector();
     check_for_wakeup();
+    m_router->call_sw_alloc();
 }
 
 bool
@@ -236,7 +237,6 @@ VCallocator_d::arbitrate_outvcs()
                         m_router->curCycle());
                     m_output_unit[outport_iter]->update_vc(
                         outvc_iter, inport, invc);
-                    m_router->swarb_req();
                     break;
                 }
             }
@@ -261,7 +261,7 @@ VCallocator_d::check_for_wakeup()
     for (int i = 0; i < m_num_inports; i++) {
         for (int j = 0; j < m_num_vcs; j++) {
             if (m_input_unit[i]->need_stage(j, VC_AB_, VA_, nextCycle)) {
-                scheduleEvent(Cycles(1));
+                m_router->vcarb_req();
                 return;
             }
         }
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
index 4db087188..996837b1b 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
@@ -55,9 +55,9 @@ VirtualChannel_d::grant_vc(int out_vc, Cycles curTime)
 {
     m_output_vc = out_vc;
     m_vc_state.first = ACTIVE_;
-    m_vc_state.second = curTime + Cycles(1);
+    m_vc_state.second = curTime;
     flit_d *t_flit = m_input_buffer->peekTopFlit();
-    t_flit->advance_stage(SA_, curTime + Cycles(1));
+    t_flit->advance_stage(SA_, curTime);
 }
 
 bool
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
index b46a095e6..b55b87feb 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
@@ -70,7 +70,7 @@ class VirtualChannel_d
     set_state(VC_state_type m_state, Cycles curTime)
     {
         m_vc_state.first = m_state;
-        m_vc_state.second = curTime + Cycles(1);
+        m_vc_state.second = curTime;
     }
 
     inline flit_d*