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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-12-31 09:32:58 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-12-31 09:32:58 -0500 |
| commit | 0fcb376e5fc6bc0a7b16dc4595d4a7e3f910cbc8 (patch) | |
| tree | 4be665e3596d9d4e193e6354c5577ee0077732da /src/mem/ruby | |
| parent | a3177645773b8eb4b835050c395554d3e2b4664a (diff) | |
| download | gem5-0fcb376e5fc6bc0a7b16dc4595d4a7e3f910cbc8.tar.xz | |
mem: Make cache terminology easier to understand
This patch changes the name of a bunch of packet flags and MSHR member
functions and variables to make the coherency protocol easier to
understand. In addition the patch adds and updates lots of
descriptions, explicitly spelling out assumptions.
The following name changes are made:
* the packet memInhibit flag is renamed to cacheResponding
* the packet sharedAsserted flag is renamed to hasSharers
* the packet NeedsExclusive attribute is renamed to NeedsWritable
* the packet isSupplyExclusive is renamed responderHadWritable
* the MSHR pendingDirty is renamed to pendingModified
The cache states, Modified, Owned, Exclusive, Shared are also called
out in the cache and MSHR code to make it easier to understand.
Diffstat (limited to 'src/mem/ruby')
| -rw-r--r-- | src/mem/ruby/system/DMASequencer.cc | 5 | ||||
| -rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 5 |
2 files changed, 6 insertions, 4 deletions
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index 3c895e627..2b65d675a 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -89,8 +89,9 @@ DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt) pkt->getAddr(), id); DMASequencer *seq = static_cast<DMASequencer *>(&owner); - if (pkt->memInhibitAsserted()) - panic("DMASequencer should never see an inhibited request\n"); + if (pkt->cacheResponding()) + panic("DMASequencer should never see a request with the " + "cacheResponding flag set\n"); assert(isPhysMemAddress(pkt->getAddr())); assert(getOffset(pkt->getAddr()) + pkt->getSize() <= diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 95a83873c..52acaf8c3 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -231,8 +231,9 @@ RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) pkt->getAddr(), id); RubyPort *ruby_port = static_cast<RubyPort *>(&owner); - if (pkt->memInhibitAsserted()) - panic("RubyPort should never see an inhibited request\n"); + if (pkt->cacheResponding()) + panic("RubyPort should never see request with the " + "cacheResponding flag set\n"); // Check for pio requests and directly send them to the dedicated // pio port. |