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authorAkash Bagdia <akash.bagdia@ARM.com>2014-11-18 14:00:48 +0000
committerAkash Bagdia <akash.bagdia@ARM.com>2014-11-18 14:00:48 +0000
commit3ee4957b4930a252c0185a6bc71bdf1c6ebc5ed9 (patch)
tree6a7e1807397f002f51fddb34568b89250fca45c8 /src/mem/ruby
parent65ecd954861aa76532ca79453afcf66a837e1fa6 (diff)
downloadgem5-3ee4957b4930a252c0185a6bc71bdf1c6ebc5ed9.tar.xz
power: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats.
Diffstat (limited to 'src/mem/ruby')
-rw-r--r--src/mem/ruby/network/garnet/BaseGarnetNetwork.cc2
-rw-r--r--src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc2
-rw-r--r--src/mem/ruby/network/simple/SimpleNetwork.cc2
-rw-r--r--src/mem/ruby/network/simple/Switch.cc2
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc2
-rw-r--r--src/mem/ruby/structures/CacheMemory.cc2
-rw-r--r--src/mem/ruby/structures/Prefetcher.cc2
-rw-r--r--src/mem/ruby/system/RubySystem.hh5
-rw-r--r--src/mem/ruby/system/Sequencer.cc2
9 files changed, 20 insertions, 1 deletions
diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc b/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
index 1213073e9..2bd2acb9f 100644
--- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
@@ -69,6 +69,8 @@ BaseGarnetNetwork::init()
void
BaseGarnetNetwork::regStats()
{
+ Network::regStats();
+
m_flits_received
.init(m_virtual_networks)
.name(name() + ".flits_received")
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
index 97bc1abdd..dab9b7dda 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
@@ -158,6 +158,8 @@ Router_d::update_sw_winner(int inport, flit_d *t_flit)
void
Router_d::regStats()
{
+ BasicRouter::regStats();
+
m_buffer_reads
.name(name() + ".buffer_reads")
.flags(Stats::nozero)
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc
index 25d0b6f4b..2fc7b6440 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -132,6 +132,8 @@ SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
void
SimpleNetwork::regStats()
{
+ Network::regStats();
+
for (MessageSizeType type = MessageSizeType_FIRST;
type < MessageSizeType_NUM; ++type) {
m_msg_counts[(unsigned int) type]
diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc
index 747884f16..78f5b609c 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -112,6 +112,8 @@ Switch::getThrottle(LinkID link_number) const
void
Switch::regStats()
{
+ BasicRouter::regStats();
+
for (int link = 0; link < m_throttles.size(); link++) {
m_throttles[link]->regStats(name());
}
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 2a53e53be..be48628e9 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -76,6 +76,8 @@ AbstractController::resetStats()
void
AbstractController::regStats()
{
+ MemObject::regStats();
+
m_fully_busy_cycles
.name(name() + ".fully_busy_cycles")
.desc("cycles for which number of transistions == max transitions")
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index f7c196119..36d109769 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -488,6 +488,8 @@ CacheMemory::isLocked(Addr address, int context)
void
CacheMemory::regStats()
{
+ SimObject::regStats();
+
m_demand_hits
.name(name() + ".demand_hits")
.desc("Number of cache demand hits")
diff --git a/src/mem/ruby/structures/Prefetcher.cc b/src/mem/ruby/structures/Prefetcher.cc
index ce6d36c04..eef51dcf7 100644
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/Prefetcher.cc
@@ -86,6 +86,8 @@ Prefetcher::~Prefetcher()
void
Prefetcher::regStats()
{
+ SimObject::regStats();
+
numMissObserved
.name(name() + ".miss_observed")
.desc("number of misses observed")
diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh
index 62330e19d..8ebd3494a 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -89,7 +89,10 @@ class RubySystem : public ClockedObject
return m_profiler;
}
- void regStats() override { m_profiler->regStats(name()); }
+ void regStats() override {
+ ClockedObject::regStats();
+ m_profiler->regStats(name());
+ }
void collateStats() { m_profiler->collateStats(); }
void resetStats() override;
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index dedade3cf..fbaad8407 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -688,6 +688,8 @@ Sequencer::evictionCallback(Addr address)
void
Sequencer::regStats()
{
+ RubyPort::regStats();
+
m_store_waiting_on_load
.name(name() + ".store_waiting_on_load")
.desc("Number of times a store aliased with a pending load")