ruby: Working M5 interface and updated Ruby interface.

This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5.  Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
  tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t

22 files changed, 353 insertions, 298 deletions

diff --git a/src/mem/ruby/common/Driver.hh b/src/mem/ruby/common/Driver.hh
index c527e7d2b..38bdbbf91 100644
--- a/src/mem/ruby/common/Driver.hh
+++ b/src/mem/ruby/common/Driver.hh
@@ -34,6 +34,7 @@
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/system/NodeID.hh"
 #include "mem/protocol/CacheRequestType.hh"
+#include "mem/packet.hh"
 
 class RubySystem;
 class SubBlock;
@@ -51,27 +52,10 @@ public:
 
   // Public Methods
   virtual void get_network_config() {}
-  virtual void hitCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread) = 0; // Called by sequencer
-  virtual void conflictCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread) { assert(0); } // Called by sequencer
+  virtual void hitCallback(Packet* pkt) = 0;
   virtual integer_t getInstructionCount(int procID) const { return 1; }
   virtual integer_t getCycleCount(int procID) const { return 1; }
-  virtual SimicsHypervisor * getHypervisor() { return NULL; }
-  virtual void notifySendNack( int procID, const Address & addr, uint64 remote_timestamp, const MachineID & remote_id) { assert(0); };   //Called by Sequencer
-  virtual void notifyReceiveNack( int procID, const Address & addr, uint64 remote_timestamp, const MachineID & remote_id) { assert(0); };   //Called by Sequencer
-  virtual void notifyReceiveNackFinal( int procID, const Address & addr) { assert(0); }; // Called by Sequencer
-  virtual void notifyTrapStart( int procID, const Address & handlerPC, int threadID, int smtThread ) { assert(0); } //called by Sequencer
-  virtual void notifyTrapComplete( int procID, const Address & newPC, int smtThread ) {assert(0);  }  // called by Sequencer
-  virtual int getOpalTransactionLevel(int procID, int thread) const {
-    cout << "mem/ruby/common/Driver.hh getOpalTransactionLevel() " << endl;
-   return 0; }  //called by Sequencer
-  virtual void addThreadDependency(int procID, int requestor_thread, int conflict_thread) const { assert(0);}
-  virtual uint64 getOpalTime(int procID) const{ return 0; }  //called by Sequencer
-  virtual uint64 getOpalTimestamp(int procID, int thread) const{
-    cout << "mem/ruby/common/Driver.hh getOpalTimestamp " << endl;
- return 0; } // called by Sequencer
-  virtual int inTransaction(int procID, int thread ) const{
-    cout << "mem/ruby/common/Driver.hh inTransaction " << endl;
-return false; } //called by Sequencer
+
   virtual void printDebug(){}  //called by Sequencer
 
   virtual void printStats(ostream& out) const = 0;
@@ -79,8 +63,6 @@ return false; } //called by Sequencer
 
   virtual void printConfig(ostream& out) const = 0;
 
-  //virtual void abortCallback(NodeID proc){}
-
   virtual integer_t readPhysicalMemory(int procID, physical_address_t address,
                                        int len ){ ASSERT(0); return 0; }
 
diff --git a/src/mem/ruby/init.cc b/src/mem/ruby/init.cc
index 6e29b1a41..bf7fcf397 100644
--- a/src/mem/ruby/init.cc
+++ b/src/mem/ruby/init.cc
@@ -40,6 +40,7 @@
 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
 #include "mem/ruby/system/System.hh"
 #include "mem/ruby/common/Debug.hh"
+#include "mem/ruby/common/Driver.hh"
 #include "mem/ruby/profiler/Profiler.hh"
 #include "mem/ruby/tester/Tester.hh"
 #include "mem/ruby/init.hh"
@@ -65,14 +66,27 @@ static void init_generate_values( void )
 }
 
 //***************************************************************************
+
 void init_variables( void )
 {
-   // allocate the "variable initialization" package
-   ruby_initvar_obj = new initvar_t( "ruby", "../../../ruby/",
-                                     global_default_param,
-                                     &init_simulator,
-                                     &init_generate_values );
+  // allocate the "variable initialization" package
+  ruby_initvar_obj = new initvar_t( "ruby", "../../../ruby/",
+                                    global_default_param,
+                                    &init_simulator,
+                                    &init_generate_values);
+}
+
+
+ /*
+void init_variables(const char* config_str )
+{
+  // allocate the "variable initialization" package
+  ruby_initvar_obj = new initvar_t( "ruby", "../../../ruby/",
+                                    config_str,
+                                    &init_simulator,
+                                    &init_generate_values );
 }
+ */
 
 void init_simulator()
 {
@@ -104,6 +118,36 @@ void init_simulator()
     cout << "Ruby initialization complete" << endl;
 }
 
+void init_simulator(Driver* _driver)
+{
+    // Set things to NULL to make sure we don't de-reference them
+    // without a seg. fault.
+    g_system_ptr = NULL;
+    g_debug_ptr = NULL;
+    g_eventQueue_ptr = NULL;
+
+    cout << "Ruby Timing Mode" << endl;
+
+
+    g_debug_ptr = new Debug( DEBUG_FILTER_STRING,
+                             DEBUG_VERBOSITY_STRING,
+                             DEBUG_START_TIME,
+                             DEBUG_OUTPUT_FILENAME );
+    RubyConfig::init();
+
+    cout << "Creating event queue..." << endl;
+    g_eventQueue_ptr = new RubyEventQueue;
+    cout << "Creating event queue done" << endl;
+
+    cout << "Creating system..." << endl;
+    cout << "  Processors: " << RubyConfig::numberOfProcessors() << endl;
+
+    g_system_ptr = new RubySystem(_driver);
+    cout << "Creating system done" << endl;
+
+    cout << "Ruby initialization complete" << endl;
+}
+
 void destroy_simulator()
 {
     cout << "Deleting system..." << endl;
@@ -122,7 +166,8 @@ void destroy_simulator()
  | M5 in phase 1 integration, and possibly afterwards, too.                |
  +-------------------------------------------------------------------------*/
 
-extern "C"
+//dsm: superfluous
+/*extern "C"
 int OnLoadRuby() {
     init_variables();
     return 0;
@@ -136,9 +181,9 @@ int OnInitRuby() {
 
 extern "C"
 int OnUnloadRuby() {
-    destroy_simulator();
-    return 0;
-}
+  destroy_simulator();
+  return 0;
+}*/
 
 /* I have to put it somewhere for now */
 void tester_main(int argc, char **argv) {
diff --git a/src/mem/ruby/init.hh b/src/mem/ruby/init.hh
index 8fec5a7c8..3299f305b 100644
--- a/src/mem/ruby/init.hh
+++ b/src/mem/ruby/init.hh
@@ -39,8 +39,12 @@
 #ifndef INIT_H
 #define INIT_H
 
+class Driver;
+
 extern void init_variables();
+//extern void init_variables(const char* config_str);
 extern void init_simulator();
+extern void init_simulator(Driver* _driver);
 extern void destroy_simulator();
 
 #endif //INIT_H
diff --git a/src/mem/ruby/interfaces/mf_api.hh b/src/mem/ruby/interfaces/mf_api.hh
deleted file mode 100644
index c04a39308..000000000
--- a/src/mem/ruby/interfaces/mf_api.hh
+++ /dev/null
@@ -1,165 +0,0 @@
-
-/*
- * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*------------------------------------------------------------------------*/
-/* Includes                                                               */
-/*------------------------------------------------------------------------*/
-
-/*------------------------------------------------------------------------*/
-/* Macro declarations                                                     */
-/*------------------------------------------------------------------------*/
-
-#ifndef _MF_MEMORY_API_H_
-#define _MF_MEMORY_API_H_
-
-#ifdef SIMICS30
-#ifndef pa_t
-typedef physical_address_t pa_t;
-typedef physical_address_t la_t;
-#endif
-#endif
-
-/**
- *  Defines types of memory requests
- */
-typedef enum OpalMemop {
-  OPAL_LOAD,
-  OPAL_STORE,
-  OPAL_IFETCH,
-  OPAL_ATOMIC,
-} OpalMemop_t;
-
-/*------------------------------------------------------------------------*/
-/* Class declaration(s)                                                   */
-/*------------------------------------------------------------------------*/
-
-/**
-* structure which provides an interface between ruby and opal.
-*/
-typedef struct mf_opal_api {
-  /**
-   * @name Methods
-   */
-  //@{
-  /**
-   * notify processor model that data from address address is available at proc
-   */
-  void (*hitCallback)( int cpuNumber, pa_t phys_address, OpalMemop_t type, int thread );
-
-  /**
-   * notify opal that ruby is loaded, or removed
-   */
-  void (*notifyCallback)( int status );
-
-  /**
-   * query for the number of instructions executed on a given processor.
-   */
-  integer_t (*getInstructionCount)( int cpuNumber );
-
-  // for printing out debug info on crash
-  void (*printDebug)();
-
-  /** query Opal for the current time */
-  uint64 (*getOpalTime)(int cpuNumber);
-
-  /** For WATTCH power stats */
-  // Called whenever L2 is accessed
-  void (*incrementL2Access)(int cpuNumber);
-  // Called whenever prefetcher is accessed
-  void (*incrementPrefetcherAccess)(int cpuNumber, int num_prefetches, int isinstr);
-
-  /* Called whenever there's an L2 miss */
-  void (*notifyL2Miss)(int cpuNumber, physical_address_t physicalAddr, OpalMemop_t type, int tagexists);
-
-  //@}
-} mf_opal_api_t;
-
-typedef struct mf_ruby_api {
-  /**
-   * @name Methods
-   */
-  //@{
-  /**
-   * Check to see if the system is ready for more requests
-   */
-  int  (*isReady)( int cpuNumber, la_t logicalAddr, pa_t physicalAddr, OpalMemop_t typeOfRequest, int thread );
-
-  /**
-   * Make a 'mandatory' request to the memory hierarchy
-   */
-  void (*makeRequest)( int cpuNumber, la_t logicalAddr, pa_t physicalAddr,
-                       int requestSize, OpalMemop_t typeOfRequest,
-                       la_t virtualPC, int isPriv, int thread);
-
-  /**
-   * Make a prefetch request to the memory hierarchy
-   */
-  void (*makePrefetch)( int cpuNumber, la_t logicalAddr, pa_t physicalAddr,
-                        int requestSize, OpalMemop_t typeOfRequest,
-                        la_t virtualPC, int isPriv, int thread);
-
-  /**
-   * Ask the memory hierarchy for 'stale' data that can be used for speculation
-   * Returns true (1) if the tag matches, false (0) if not.
-   */
-  int (*staleDataRequest)( int cpuNumber, pa_t physicalAddr,
-                           int requestSize, int8 *buffer );
-
-  /**
-   * Advance ruby's cycle time one step
-   */
-  void (*advanceTime)( void );
-
-  /**
-   * Get ruby's cycle time count.
-   */
-  uint64 (*getTime)( void );
-
-  /** prints Ruby's outstanding request table */
-  void (*printProgress)(int cpuNumber);
-
-  /**
-   * notify ruby that opal is loaded, or removed
-   */
-  void (*notifyCallback)( int status );
-
-  // Returns the number of outstanding request
-  int (*getNumberOutstanding)(int cpuNumber);
-
-  // Returns the number of outstanding demand requests
-  int (*getNumberOutstandingDemand)(int cpuNumber );
-
-  // Returns the number of outstanding prefetch request
-  int (*getNumberOutstandingPrefetch)(int cpuNumber );
-
-
-  //@}
-} mf_ruby_api_t;
-
-#endif //_MF_MEMORY_API_H_
diff --git a/src/mem/ruby/recorder/TraceRecord.cc b/src/mem/ruby/recorder/TraceRecord.cc
index ab1069582..31b83690e 100644
--- a/src/mem/ruby/recorder/TraceRecord.cc
+++ b/src/mem/ruby/recorder/TraceRecord.cc
@@ -37,6 +37,7 @@
 #include "mem/ruby/system/System.hh"
 #include "mem/ruby/slicc_interface/AbstractChip.hh"
 #include "mem/protocol/CacheMsg.hh"
+#include "mem/packet.hh"
 
 TraceRecord::TraceRecord(NodeID id, const Address& data_addr, const Address& pc_addr, CacheRequestType type, Time time)
 {
@@ -78,14 +79,27 @@ void TraceRecord::issueRequest() const
   Sequencer* sequencer_ptr = chip_ptr->getSequencer((m_node_num/RubyConfig::numberofSMTThreads())%RubyConfig::numberOfProcsPerChip());
   assert(sequencer_ptr != NULL);
 
-  CacheMsg request(m_data_address, m_data_address, m_type, m_pc_address, AccessModeType_UserMode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */);
+  Addr data_addr = m_data_address.getAddress();
+  Addr pc_addr = m_pc_address.getAddress();
+  Request request(0, data_addr, 0, Flags<unsigned int>(Request::PREFETCH), pc_addr, m_node_num, 0);
+  MemCmd::Command command;
+  if (m_type == CacheRequestType_LD || m_type == CacheRequestType_IFETCH)
+    command = MemCmd::ReadReq;
+  else if (m_type == CacheRequestType_ST)
+    command = MemCmd::WriteReq;
+  else if (m_type == CacheRequestType_ATOMIC)
+    command = MemCmd::SwapReq; // TODO -- differentiate between atomic types
+  else
+    assert(false);
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
 
   // Clear out the sequencer
   while (!sequencer_ptr->empty()) {
     g_eventQueue_ptr->triggerEvents(g_eventQueue_ptr->getTime() + 100);
   }
 
-  sequencer_ptr->makeRequest(request);
+  sequencer_ptr->makeRequest(&pkt);
 
   // Clear out the sequencer
   while (!sequencer_ptr->empty()) {
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 4217a8685..a8306c06f 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -42,7 +42,9 @@
 #include "mem/ruby/common/Global.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
-#include "mem/ruby/recorder/CacheRecorder.hh"
+
+//dsm: PRUNED
+//#include "mem/ruby/recorder/CacheRecorder.hh"
 #include "mem/protocol/CacheRequestType.hh"
 #include "mem/gems_common/Vector.hh"
 #include "mem/ruby/common/DataBlock.hh"
@@ -142,6 +144,8 @@ private:
   int m_cache_num_sets;
   int m_cache_num_set_bits;
   int m_cache_assoc;
+
+  bool is_locked; // for LL/SC
 };
 
 // Output operator declaration
@@ -489,7 +493,10 @@ template<class ENTRY>
 inline
 void CacheMemory<ENTRY>::recordCacheContents(CacheRecorder& tr) const
 {
-  for (int i = 0; i < m_cache_num_sets; i++) {
+//dsm: Uses CacheRecorder, PRUNED
+assert(false);
+
+/*  for (int i = 0; i < m_cache_num_sets; i++) {
     for (int j = 0; j < m_cache_assoc; j++) {
       AccessPermission perm = m_cache[i][j].m_Permission;
       CacheRequestType request_type = CacheRequestType_NULL;
@@ -508,7 +515,7 @@ void CacheMemory<ENTRY>::recordCacheContents(CacheRecorder& tr) const
                      Address(0), request_type, m_replacementPolicy_ptr->getLastAccess(i, j));
       }
     }
-  }
+  }*/
 }
 
 template<class ENTRY>
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index fa5b75eb3..82eef2901 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -46,6 +46,7 @@
 #include "mem/ruby/common/SubBlock.hh"
 #include "mem/protocol/Protocol.hh"
 #include "mem/gems_common/Map.hh"
+#include "mem/packet.hh"
 
 Sequencer::Sequencer(AbstractChip* chip_ptr, int version) {
   m_chip_ptr = chip_ptr;
@@ -58,6 +59,8 @@ Sequencer::Sequencer(AbstractChip* chip_ptr, int version) {
   m_writeRequestTable_ptr = new Map<Address, CacheMsg>*[smt_threads];
   m_readRequestTable_ptr = new Map<Address, CacheMsg>*[smt_threads];
 
+  m_packetTable_ptr = new Map<Address, Packet*>;
+
   for(int p=0; p < smt_threads; ++p){
     m_writeRequestTable_ptr[p] = new Map<Address, CacheMsg>;
     m_readRequestTable_ptr[p] = new Map<Address, CacheMsg>;
@@ -603,7 +606,8 @@ void Sequencer::hitCallback(const CacheMsg& request, DataBlock& data, GenericMac
     (type == CacheRequestType_ATOMIC);
 
   if (TSO && write) {
-    m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->callBack(line_address(request.getAddress()), data);
+    m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->callBack(line_address(request.getAddress()), data,
+                                                               m_packetTable_ptr->lookup(request.getAddress()));
   } else {
 
     // Copy the correct bytes out of the cache line into the subblock
@@ -616,7 +620,23 @@ void Sequencer::hitCallback(const CacheMsg& request, DataBlock& data, GenericMac
     }
 
     // Call into the Driver and let it read and/or modify the sub-block
-    g_system_ptr->getDriver()->hitCallback(m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version, subblock, type, threadID);
+    Packet* pkt = m_packetTable_ptr->lookup(request.getAddress());
+
+    // update data if this is a store/atomic
+
+    /*
+    if (pkt->req->isCondSwap()) {
+      L1Cache_Entry entry = m_L1Cache_vec[m_version]->lookup(Address(pkt->req->physAddr()));
+      DataBlk datablk = entry->getDataBlk();
+      uint8_t *orig_data = datablk.getArray();
+      if ( datablk.equal(pkt->req->getExtraData()) )
+        datablk->setArray(pkt->getData());
+      pkt->setData(orig_data);
+    }
+    */
+
+    g_system_ptr->getDriver()->hitCallback(pkt);
+    m_packetTable_ptr->remove(request.getAddress());
 
     // If the request was a Store or Atomic, apply the changes in the SubBlock to the DataBlock
     // (This is only triggered for the non-TSO case)
@@ -632,6 +652,7 @@ void Sequencer::printDebug(){
   g_system_ptr->getDriver()->printDebug();
 }
 
+//dsm: breaks build, delayed
 // Returns true if the sequencer already has a load or store outstanding
 bool
 Sequencer::isReady(const Packet* pkt) const
@@ -665,7 +686,7 @@ Sequencer::isReady(const Packet* pkt) const
                    Address(logical_addr),   // Virtual Address
                    thread              // SMT thread
                    );
-  isReady(request);
+  return isReady(request);
 }
 
 bool
@@ -701,26 +722,36 @@ Sequencer::isReady(const CacheMsg& request) const
   return true;
 }
 
-// Called by Driver
+//dsm: breaks build, delayed
+// Called by Driver (Simics or Tester).
 void
-Sequencer::makeRequest(const Packet* pkt, void* data)
+Sequencer::makeRequest(Packet* pkt)
 {
   int cpu_number = pkt->req->contextId();
   la_t logical_addr = pkt->req->getVaddr();
   pa_t physical_addr = pkt->req->getPaddr();
   int request_size = pkt->getSize();
   CacheRequestType type_of_request;
+  PrefetchBit prefetch;
+  bool write = false;
   if ( pkt->req->isInstFetch() ) {
     type_of_request = CacheRequestType_IFETCH;
   } else if ( pkt->req->isLocked() || pkt->req->isSwap() ) {
     type_of_request = CacheRequestType_ATOMIC;
+    write = true;
   } else if ( pkt->isRead() ) {
     type_of_request = CacheRequestType_LD;
   } else if ( pkt->isWrite() ) {
     type_of_request = CacheRequestType_ST;
+    write = true;
   } else {
     assert(false);
   }
+  if (pkt->req->isPrefetch()) {
+    prefetch = PrefetchBit_Yes;
+  } else {
+    prefetch = PrefetchBit_No;
+  }
   la_t virtual_pc = pkt->req->getPC();
   int isPriv = false;  // TODO: get permission data
   int thread = pkt->req->threadId();
@@ -733,28 +764,21 @@ Sequencer::makeRequest(const Packet* pkt, void* data)
                    Address(virtual_pc),
                    access_mode,   // User/supervisor mode
                    request_size,   // Size in bytes of request
-                   PrefetchBit_No, // Not a prefetch
+                   prefetch,
                    0,              // Version number
                    Address(logical_addr),   // Virtual Address
                    thread         // SMT thread
                    );
-  makeRequest(request);
-}
-
-void
-Sequencer::makeRequest(const CacheMsg& request)
-{
-  bool write = (request.getType() == CacheRequestType_ST) ||
-    (request.getType() == CacheRequestType_ATOMIC);
 
-  if (TSO && (request.getPrefetch() == PrefetchBit_No) && write) {
+  if ( TSO && write && !pkt->req->isPrefetch() ) {
     assert(m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->isReady());
-    m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->insertStore(request);
+    m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->insertStore(pkt, request);
     return;
   }
 
-  bool hit = doRequest(request);
+  m_packetTable_ptr->insert(Address( physical_addr ), pkt);
 
+  doRequest(request);
 }
 
 bool Sequencer::doRequest(const CacheMsg& request) {
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index f4cc03131..d34a2fd3e 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -45,13 +45,13 @@
 #include "mem/protocol/GenericMachineType.hh"
 #include "mem/protocol/PrefetchBit.hh"
 #include "mem/gems_common/Map.hh"
-#include "mem/packet.hh"
 
 class DataBlock;
 class AbstractChip;
 class CacheMsg;
 class Address;
 class MachineID;
+class Packet;
 
 class Sequencer : public Consumer {
 public:
@@ -103,8 +103,7 @@ public:
   void printDebug();
 
   // called by Tester or Simics
-  void makeRequest(const Packet* pkt, void* data);
-  void makeRequest(const CacheMsg& request); // depricate this function
+  void makeRequest(Packet* pkt);
   bool doRequest(const CacheMsg& request);
   void issueRequest(const CacheMsg& request);
   bool isReady(const Packet* pkt) const;
@@ -143,6 +142,9 @@ private:
   // One request table per SMT thread
   Map<Address, CacheMsg>** m_writeRequestTable_ptr;
   Map<Address, CacheMsg>** m_readRequestTable_ptr;
+
+  Map<Address, Packet*>* m_packetTable_ptr;
+
   // Global outstanding request count, across all request tables
   int m_outstanding_count;
   bool m_deadlock_check_scheduled;
diff --git a/src/mem/ruby/system/StoreBuffer.cc b/src/mem/ruby/system/StoreBuffer.cc
index 7f43771f3..280decdd8 100644
--- a/src/mem/ruby/system/StoreBuffer.cc
+++ b/src/mem/ruby/system/StoreBuffer.cc
@@ -44,6 +44,7 @@
 #include "mem/ruby/system/Sequencer.hh"
 #include "mem/ruby/common/SubBlock.hh"
 #include "mem/ruby/profiler/Profiler.hh"
+#include "mem/packet.hh"
 
 // *** Begin Helper class ***
 struct StoreBufferEntry {
@@ -150,7 +151,8 @@ void StoreBuffer::printConfig(ostream& out)
 
 // Handle an incoming store request, this method is responsible for
 // calling hitCallback as needed
-void StoreBuffer::insertStore(const CacheMsg& request)
+void
+StoreBuffer::insertStore(Packet* pkt, const CacheMsg& request)
 {
   Address addr = request.getAddress();
   CacheRequestType type = request.getType();
@@ -173,7 +175,7 @@ void StoreBuffer::insertStore(const CacheMsg& request)
   // Perform the hit-callback for the store
   SubBlock subblock(addr, size);
   if(type == CacheRequestType_ST) {
-    g_system_ptr->getDriver()->hitCallback(m_chip_ptr->getID(), subblock, type, threadID);
+    g_system_ptr->getDriver()->hitCallback(pkt);
     assert(subblock.getSize() != 0);
   } else {
     // wait to perform the hitCallback until later for Atomics
@@ -181,9 +183,9 @@ void StoreBuffer::insertStore(const CacheMsg& request)
 
   // Perform possible pre-fetch
   if(!isEmpty()) {
-    CacheMsg new_request = request;
-    new_request.getPrefetch() = PrefetchBit_Yes;
-    m_chip_ptr->getSequencer(m_version)->makeRequest(new_request);
+    Packet new_pkt(pkt);
+    pkt->req->setFlags(Request::PREFETCH);
+    m_chip_ptr->getSequencer(m_version)->makeRequest(&new_pkt);
   }
 
   // Update the StoreCache
@@ -200,7 +202,7 @@ void StoreBuffer::insertStore(const CacheMsg& request)
   processHeadOfQueue();
 }
 
-void StoreBuffer::callBack(const Address& addr, DataBlock& data)
+void StoreBuffer::callBack(const Address& addr, DataBlock& data, Packet* pkt)
 {
   DEBUG_MSG(STOREBUFFER_COMP, MedPrio, "callBack");
   DEBUG_EXPR(STOREBUFFER_COMP, MedPrio, g_eventQueue_ptr->getTime());
@@ -220,7 +222,7 @@ void StoreBuffer::callBack(const Address& addr, DataBlock& data)
   } else {
     // We waited to perform the hitCallback until now for Atomics
     peek().m_subblock.mergeFrom(data);  // copy the correct bytes from DataBlock into the SubBlock for the Load part of the atomic Load/Store
-    g_system_ptr->getDriver()->hitCallback(m_chip_ptr->getID(), peek().m_subblock, type, threadID);
+    g_system_ptr->getDriver()->hitCallback(pkt);
     m_seen_atomic = false;
 
     /// FIXME - record the time spent in the store buffer - split out ST vs ATOMIC
diff --git a/src/mem/ruby/system/StoreBuffer.hh b/src/mem/ruby/system/StoreBuffer.hh
index 2fae52643..2c9283f4b 100644
--- a/src/mem/ruby/system/StoreBuffer.hh
+++ b/src/mem/ruby/system/StoreBuffer.hh
@@ -49,6 +49,7 @@ class DataBlock;
 class SubBlock;
 class StoreBufferEntry;
 class AbstractChip;
+class Packet;
 
 template <class TYPE> class Vector;
 
@@ -62,8 +63,8 @@ public:
 
   // Public Methods
   void wakeup(); // Used only for deadlock detection
-  void callBack(const Address& addr, DataBlock& data);
-  void insertStore(const CacheMsg& request);
+  void callBack(const Address& addr, DataBlock& data, Packet* pkt);
+  void insertStore(Packet* pkt, const CacheMsg& request);
   void updateSubBlock(SubBlock& sub_block) const { m_store_cache.update(sub_block); }
   bool trySubBlock(const SubBlock& sub_block) const { assert(isReady()); return m_store_cache.check(sub_block); }
   void print(ostream& out) const;
diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc
index ae77d2a85..877a894fc 100644
--- a/src/mem/ruby/system/System.cc
+++ b/src/mem/ruby/system/System.cc
@@ -46,13 +46,49 @@
 #include "mem/protocol/Chip.hh"
 //#include "mem/ruby/recorder/Tracer.hh"
 #include "mem/protocol/Protocol.hh"
-//#include "XactIsolationChecker.hh"  // gem5:Arka for decomissioning of log_tm
-//#include "XactCommitArbiter.hh"
-//#include "XactVisualizer.hh"
-#include "mem/ruby/interfaces/M5Driver.hh"
 
 RubySystem::RubySystem()
 {
+  init();
+  m_preinitialized_driver = false;
+  createDriver();
+
+ /*  gem5:Binkert for decomissiong of tracer
+     m_tracer_ptr = new Tracer;
+ */
+
+ /*  gem5:Arka for decomissiong of log_tm
+  if (XACT_MEMORY) {
+    m_xact_isolation_checker = new XactIsolationChecker;
+    m_xact_commit_arbiter    = new XactCommitArbiter;
+    m_xact_visualizer        = new XactVisualizer;
+  }
+*/
+}
+
+RubySystem::RubySystem(Driver* _driver)
+{
+  init();
+  m_preinitialized_driver = true;
+  m_driver_ptr = _driver;
+}
+
+RubySystem::~RubySystem()
+{
+  for (int i = 0; i < m_chip_vector.size(); i++) {
+    delete m_chip_vector[i];
+  }
+  if (!m_preinitialized_driver)
+    delete m_driver_ptr;
+  delete m_network_ptr;
+  delete m_profiler_ptr;
+ /*  gem5:Binkert for decomissiong of tracer
+     delete m_tracer_ptr;
+ */
+}
+
+void RubySystem::init()
+{
   DEBUG_MSG(SYSTEM_COMP, MedPrio,"initializing");
 
   m_driver_ptr = NULL;
@@ -101,44 +137,19 @@ RubySystem::RubySystem()
     }
   }
 #endif
+  DEBUG_MSG(SYSTEM_COMP, MedPrio,"finished initializing");
+  DEBUG_NEWLINE(SYSTEM_COMP, MedPrio);
+}
 
+void RubySystem::createDriver()
+{
     if (g_SYNTHETIC_DRIVER && !g_DETERMINISTIC_DRIVER) {
       cerr << "Creating Synthetic Driver" << endl;
       m_driver_ptr = new SyntheticDriver(this);
     } else if (!g_SYNTHETIC_DRIVER && g_DETERMINISTIC_DRIVER) {
       cerr << "Creating Deterministic Driver" << endl;
       m_driver_ptr = new DeterministicDriver(this);
-    } else {
-      cerr << "Creating M5 Driver" << endl;
-      m_driver_ptr = new M5Driver(this);
     }
- /*  gem5:Binkert for decomissiong of tracer
-     m_tracer_ptr = new Tracer;
- */
-
- /*  gem5:Arka for decomissiong of log_tm
-  if (XACT_MEMORY) {
-    m_xact_isolation_checker = new XactIsolationChecker;
-    m_xact_commit_arbiter    = new XactCommitArbiter;
-    m_xact_visualizer        = new XactVisualizer;
-  }
-*/
-  DEBUG_MSG(SYSTEM_COMP, MedPrio,"finished initializing");
-  DEBUG_NEWLINE(SYSTEM_COMP, MedPrio);
-
-}
-
-RubySystem::~RubySystem()
-{
-  for (int i = 0; i < m_chip_vector.size(); i++) {
-    delete m_chip_vector[i];
-  }
-  delete m_driver_ptr;
-  delete m_network_ptr;
-  delete m_profiler_ptr;
- /*  gem5:Binkert for decomissiong of tracer
-     delete m_tracer_ptr;
- */
 }
 
 void RubySystem::printConfig(ostream& out) const
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index 12063eeed..8679b55c3 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -63,6 +63,7 @@ class RubySystem {
 public:
   // Constructors
   RubySystem();
+  RubySystem(Driver* _driver); // used when driver is already instantiated (e.g. M5's RubyMem)
 
   // Destructor
   ~RubySystem();
@@ -98,6 +99,8 @@ public:
 
 private:
   // Private Methods
+  void init();
+  void createDriver();
 
   // Private copy constructor and assignment operator
   RubySystem(const RubySystem& obj);
@@ -107,6 +110,7 @@ private:
   Network* m_network_ptr;
   Vector<AbstractChip*> m_chip_vector;
   Profiler* m_profiler_ptr;
+  bool m_preinitialized_driver;
   Driver* m_driver_ptr;
   Tracer* m_tracer_ptr;
   XactIsolationChecker *m_xact_isolation_checker;
diff --git a/src/mem/ruby/tester/Check.cc b/src/mem/ruby/tester/Check.cc
index ea26489a3..b9e7e3c10 100644
--- a/src/mem/ruby/tester/Check.cc
+++ b/src/mem/ruby/tester/Check.cc
@@ -37,6 +37,7 @@
 #include "mem/ruby/system/System.hh"
 #include "mem/ruby/common/SubBlock.hh"
 #include "mem/protocol/Chip.hh"
+#include "mem/packet.hh"
 
 Check::Check(const Address& address, const Address& pc)
 {
@@ -84,10 +85,29 @@ void Check::initiatePrefetch(Sequencer* targetSequencer_ptr)
   } else {
     type = CacheRequestType_ST;
   }
+
+  Addr data_addr = m_address.getAddress();
+  Addr pc_addr = m_pc.getAddress();
+  Request request(0, data_addr, 0, Flags<unsigned int>(Request::PREFETCH), pc_addr, 0, 0);
+  MemCmd::Command command;
+  if (type == CacheRequestType_IFETCH) {
+    command = MemCmd::ReadReq;
+    request.setFlags(Request::INST_FETCH);
+  } else if (type == CacheRequestType_LD || type == CacheRequestType_IFETCH) {
+    command = MemCmd::ReadReq;
+  } else if (type == CacheRequestType_ST) {
+    command = MemCmd::WriteReq;
+  } else if (type == CacheRequestType_ATOMIC) {
+    command = MemCmd::SwapReq; // TODO -- differentiate between atomic types
+  } else {
+    assert(false);
+  }
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
   assert(targetSequencer_ptr != NULL);
-  CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */);
-  if (targetSequencer_ptr->isReady(request)) {
-    targetSequencer_ptr->makeRequest(request);
+  if (targetSequencer_ptr->isReady(&pkt)) {
+    targetSequencer_ptr->makeRequest(&pkt);
   }
 }
 
@@ -109,15 +129,34 @@ void Check::initiateAction()
     type = CacheRequestType_ATOMIC;
   }
 
-  CacheMsg request(Address(m_address.getAddress()+m_store_count), Address(m_address.getAddress()+m_store_count), type, m_pc, m_access_mode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */);
+  Addr data_addr = m_address.getAddress()+m_store_count;
+  Addr pc_addr = m_pc.getAddress();
+  Request request(0, data_addr, 1, Flags<unsigned int>(), pc_addr, 0, 0);
+  MemCmd::Command command;
+  if (type == CacheRequestType_IFETCH) {
+    command = MemCmd::ReadReq;
+    request.setFlags(Request::INST_FETCH);
+  } else if (type == CacheRequestType_LD || type == CacheRequestType_IFETCH) {
+    command = MemCmd::ReadReq;
+  } else if (type == CacheRequestType_ST) {
+    command = MemCmd::WriteReq;
+  } else if (type == CacheRequestType_ATOMIC) {
+    command = MemCmd::SwapReq; // TODO -- differentiate between atomic types
+  } else {
+    assert(false);
+  }
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
   Sequencer* sequencer_ptr = initiatingSequencer();
-  if (sequencer_ptr->isReady(request) == false) {
+  if (sequencer_ptr->isReady(&pkt) == false) {
     DEBUG_MSG(TESTER_COMP, MedPrio, "failed to initiate action - sequencer not ready\n");
   } else {
     DEBUG_MSG(TESTER_COMP, MedPrio, "initiating action - successful\n");
     DEBUG_EXPR(TESTER_COMP, MedPrio, m_status);
     m_status = TesterStatus_Action_Pending;
-    sequencer_ptr->makeRequest(request);
+
+    sequencer_ptr->makeRequest(&pkt);
   }
   DEBUG_EXPR(TESTER_COMP, MedPrio, m_status);
 }
@@ -132,15 +171,35 @@ void Check::initiateCheck()
     type = CacheRequestType_IFETCH;
   }
 
-  CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, CHECK_SIZE, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */);
+
+  Addr data_addr = m_address.getAddress()+m_store_count;
+  Addr pc_addr = m_pc.getAddress();
+  Request request(0, data_addr, CHECK_SIZE, Flags<unsigned int>(), pc_addr, 0, 0);
+  MemCmd::Command command;
+  if (type == CacheRequestType_IFETCH) {
+    command = MemCmd::ReadReq;
+    request.setFlags(Request::INST_FETCH);
+  } else if (type == CacheRequestType_LD || type == CacheRequestType_IFETCH) {
+    command = MemCmd::ReadReq;
+  } else if (type == CacheRequestType_ST) {
+    command = MemCmd::WriteReq;
+  } else if (type == CacheRequestType_ATOMIC) {
+    command = MemCmd::SwapReq; // TODO -- differentiate between atomic types
+  } else {
+    assert(false);
+  }
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
   Sequencer* sequencer_ptr = initiatingSequencer();
-  if (sequencer_ptr->isReady(request) == false) {
+  if (sequencer_ptr->isReady(&pkt) == false) {
     DEBUG_MSG(TESTER_COMP, MedPrio, "failed to initiate check - sequencer not ready\n");
   } else {
     DEBUG_MSG(TESTER_COMP, MedPrio, "initiating check - successful\n");
     DEBUG_MSG(TESTER_COMP, MedPrio, m_status);
     m_status = TesterStatus_Check_Pending;
-    sequencer_ptr->makeRequest(request);
+
+    sequencer_ptr->makeRequest(&pkt);
   }
   DEBUG_MSG(TESTER_COMP, MedPrio, m_status);
 }
diff --git a/src/mem/ruby/tester/DetermGETXGenerator.cc b/src/mem/ruby/tester/DetermGETXGenerator.cc
index d496cbe3a..e4d8addd2 100644
--- a/src/mem/ruby/tester/DetermGETXGenerator.cc
+++ b/src/mem/ruby/tester/DetermGETXGenerator.cc
@@ -44,6 +44,7 @@
 #include "mem/ruby/common/SubBlock.hh"
 #include "mem/ruby/tester/DeterministicDriver.hh"
 #include "mem/protocol/Chip.hh"
+#include "mem/packet.hh"
 
 DetermGETXGenerator::DetermGETXGenerator(NodeID node, DeterministicDriver& driver) :
   m_driver(driver)
@@ -137,7 +138,15 @@ void DetermGETXGenerator::pickAddress()
 void DetermGETXGenerator::initiateStore()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
+
+  Addr data_addr = m_address.getAddress();
+  Request request(0, data_addr, 1, Flags<unsigned int>(), 3, 0, 0);
+  MemCmd::Command command;
+  command = MemCmd::WriteReq;
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
+  sequencer()->makeRequest(&pkt);
 }
 
 Sequencer* DetermGETXGenerator::sequencer() const
diff --git a/src/mem/ruby/tester/DetermInvGenerator.cc b/src/mem/ruby/tester/DetermInvGenerator.cc
index 89d70d91a..bafaa18ae 100644
--- a/src/mem/ruby/tester/DetermInvGenerator.cc
+++ b/src/mem/ruby/tester/DetermInvGenerator.cc
@@ -179,13 +179,30 @@ void DetermInvGenerator::pickLoadAddress()
 void DetermInvGenerator::initiateLoad()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Load");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
+
+  Addr data_addr = m_address.getAddress();
+  Request request(0, data_addr, 1, Flags<unsigned int>(), 1, 0, 0);
+  MemCmd::Command command;
+  command = MemCmd::ReadReq;
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
+  sequencer()->makeRequest(&pkt);
+
 }
 
 void DetermInvGenerator::initiateStore()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
+
+  Addr data_addr = m_address.getAddress();
+  Request request(0, data_addr, 1, Flags<unsigned int>(), 3, 0, 0);
+  MemCmd::Command command;
+  command = MemCmd::WriteReq;
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
+  sequencer()->makeRequest(&pkt);
 }
 
 Sequencer* DetermInvGenerator::sequencer() const
diff --git a/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc b/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
index 67fca6fe0..5adc7aa5c 100644
--- a/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
+++ b/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
@@ -135,7 +135,16 @@ void DetermSeriesGETSGenerator::pickAddress()
 void DetermSeriesGETSGenerator::initiateLoad()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Load");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_IFETCH, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
+
+  Addr data_addr = m_address.getAddress();
+  Request request(0, data_addr, 1, Flags<unsigned int>(), 3, 0, 0);
+  MemCmd::Command command;
+  command = MemCmd::ReadReq;
+  request.setFlags(Request::INST_FETCH);
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
+  sequencer()->makeRequest(&pkt);
 }
 
 Sequencer* DetermSeriesGETSGenerator::sequencer() const
diff --git a/src/mem/ruby/tester/DeterministicDriver.cc b/src/mem/ruby/tester/DeterministicDriver.cc
index 7b7d0c9d2..762672118 100644
--- a/src/mem/ruby/tester/DeterministicDriver.cc
+++ b/src/mem/ruby/tester/DeterministicDriver.cc
@@ -42,6 +42,7 @@
 #include "mem/ruby/tester/DetermSeriesGETSGenerator.hh"
 #include "mem/ruby/common/SubBlock.hh"
 #include "mem/protocol/Chip.hh"
+#include "mem/packet.hh"
 
 DeterministicDriver::DeterministicDriver(RubySystem* sys_ptr)
 {
@@ -99,13 +100,17 @@ DeterministicDriver::~DeterministicDriver()
   }
 }
 
-void DeterministicDriver::hitCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread)
+void
+DeterministicDriver::hitCallback(Packet * pkt)
 {
-  DEBUG_EXPR(TESTER_COMP, MedPrio, data);
-
+  NodeID proc = pkt->req->contextId();
+  SubBlock data(Address(pkt->getAddr()), pkt->req->getSize());
+  if (pkt->hasData()) {
+    for (int i = 0; i < pkt->req->getSize(); i++) {
+      data.setByte(i, *(pkt->getPtr<uint8>()+i));
+    }
+  }
   m_generator_vector[proc]->performCallback(proc, data);
-
-  // Mark that we made progress
   m_last_progress_vector[proc] = g_eventQueue_ptr->getTime();
 }
 
diff --git a/src/mem/ruby/tester/DeterministicDriver.hh b/src/mem/ruby/tester/DeterministicDriver.hh
index d253b7e51..710da7922 100644
--- a/src/mem/ruby/tester/DeterministicDriver.hh
+++ b/src/mem/ruby/tester/DeterministicDriver.hh
@@ -44,6 +44,7 @@
 
 class RubySystem;
 class SpecifiedGenerator;
+class Packet;
 
 class DeterministicDriver : public Driver, public Consumer {
 public:
@@ -69,7 +70,7 @@ public:
   void recordLoadLatency(Time time);
   void recordStoreLatency(Time time);
 
-  void hitCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread);
+  void hitCallback(Packet* pkt);
   void wakeup();
   void printStats(ostream& out) const;
   void clearStats() {}
diff --git a/src/mem/ruby/tester/RequestGenerator.cc b/src/mem/ruby/tester/RequestGenerator.cc
index c1772f905..4ee24544f 100644
--- a/src/mem/ruby/tester/RequestGenerator.cc
+++ b/src/mem/ruby/tester/RequestGenerator.cc
@@ -169,19 +169,43 @@ void RequestGenerator::pickAddress()
 void RequestGenerator::initiateTest()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Test");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
+
+  Addr data_addr = m_address.getAddress();
+  Request request(0, data_addr, 1, Flags<unsigned int>(), 1, 0, 0);
+  MemCmd::Command command;
+  command = MemCmd::ReadReq;
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
+  sequencer()->makeRequest(&pkt);
 }
 
 void RequestGenerator::initiateSwap()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Swap");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ATOMIC, Address(2), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
+
+  Addr data_addr = m_address.getAddress();
+  Request request(0, data_addr, 1, Flags<unsigned int>(), 2, 0, 0);
+  MemCmd::Command command;
+  command = MemCmd::SwapReq;
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
+  sequencer()->makeRequest(&pkt);
 }
 
 void RequestGenerator::initiateRelease()
 {
   DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Release");
-  sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
+
+  Addr data_addr = m_address.getAddress();
+  Request request(0, data_addr, 1, Flags<unsigned int>(), 3, 0, 0);
+  MemCmd::Command command;
+  command = MemCmd::WriteReq;
+
+  Packet pkt(&request, command, 0); // TODO -- make dest a real NodeID
+
+  sequencer()->makeRequest(&pkt);
 }
 
 Sequencer* RequestGenerator::sequencer() const
diff --git a/src/mem/ruby/tester/SyntheticDriver.cc b/src/mem/ruby/tester/SyntheticDriver.cc
index 081fc9d5e..f19baa202 100644
--- a/src/mem/ruby/tester/SyntheticDriver.cc
+++ b/src/mem/ruby/tester/SyntheticDriver.cc
@@ -75,18 +75,17 @@ SyntheticDriver::~SyntheticDriver()
   }
 }
 
-void SyntheticDriver::hitCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread)
+void
+SyntheticDriver::hitCallback(Packet * pkt)
 {
-  DEBUG_EXPR(TESTER_COMP, MedPrio, data);
-  //cout << "  " << proc << " in S.D. hitCallback" << endl;
-  if(XACT_MEMORY){
-    //XactRequestGenerator* reqGen = static_cast<XactRequestGenerator*>(m_request_generator_vector[proc]);
-    //reqGen->performCallback(proc, data);
-  } else {
-    m_request_generator_vector[proc]->performCallback(proc, data);
+  NodeID proc = pkt->req->contextId();
+  SubBlock data(Address(pkt->getAddr()), pkt->req->getSize());
+  if (pkt->hasData()) {
+    for (int i = 0; i < pkt->req->getSize(); i++) {
+      data.setByte(i, *(pkt->getPtr<uint8>()+i));
+    }
   }
-
-  // Mark that we made progress
+  m_request_generator_vector[proc]->performCallback(proc, data);
   m_last_progress_vector[proc] = g_eventQueue_ptr->getTime();
 }
 
diff --git a/src/mem/ruby/tester/SyntheticDriver.hh b/src/mem/ruby/tester/SyntheticDriver.hh
index dc0f1be1d..18c463e88 100644
--- a/src/mem/ruby/tester/SyntheticDriver.hh
+++ b/src/mem/ruby/tester/SyntheticDriver.hh
@@ -60,7 +60,7 @@ public:
   void recordSwapLatency(Time time);
   void recordReleaseLatency(Time time);
 
-  void hitCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread);
+  void hitCallback(Packet* pkt);
   void conflictCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread) {assert(0);}
   void abortCallback(NodeID proc, SubBlock& data, CacheRequestType type, int thread);
   void wakeup();
diff --git a/src/mem/ruby/tester/main.cc b/src/mem/ruby/tester/main.cc
index 5e77488e9..ba835b488 100644
--- a/src/mem/ruby/tester/main.cc
+++ b/src/mem/ruby/tester/main.cc
@@ -35,7 +35,7 @@
 #include "mem/ruby/tester/main.hh"
 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
 #include "mem/ruby/config/RubyConfig.hh"
-#include "mem/ruby/tester/test_framework.hh"
+//#include "mem/ruby/tester/test_framework.hh"
 
 // *******************
 // *** tester main ***
@@ -43,5 +43,6 @@
 
 int main(int argc, char *argv[])
 {
-  tester_main(argc, argv);
+    //dsm: PRUNED
+    //tester_main(argc, argv);
 }