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authorDavid Hashe <david.hashe@amd.com>2015-07-20 09:15:18 -0500
committerDavid Hashe <david.hashe@amd.com>2015-07-20 09:15:18 -0500
commitc4ffd4989c35a4afea1097fec97ac5bcd52974b3 (patch)
tree04796c3fd4ba631f20d47f17906b47c7bbb84a59 /src/mem/ruby
parent967cfa939afca4a5752ce9c1d64d5c51092e7f1a (diff)
downloadgem5-c4ffd4989c35a4afea1097fec97ac5bcd52974b3.tar.xz
ruby: expose access permission to replacement policies
This patch adds support that allows the replacement policy to identify each cache block's access permission. This information can be useful when making replacement decisions.
Diffstat (limited to 'src/mem/ruby')
-rw-r--r--src/mem/ruby/structures/AbstractReplacementPolicy.hh5
-rw-r--r--src/mem/ruby/structures/CacheMemory.cc13
-rw-r--r--src/mem/ruby/structures/CacheMemory.hh2
3 files changed, 20 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/AbstractReplacementPolicy.hh b/src/mem/ruby/structures/AbstractReplacementPolicy.hh
index d007c98c8..03ef0d2fd 100644
--- a/src/mem/ruby/structures/AbstractReplacementPolicy.hh
+++ b/src/mem/ruby/structures/AbstractReplacementPolicy.hh
@@ -34,6 +34,8 @@
#include "params/ReplacementPolicy.hh"
#include "sim/sim_object.hh"
+class CacheMemory;
+
class AbstractReplacementPolicy : public SimObject
{
public:
@@ -52,6 +54,9 @@ class AbstractReplacementPolicy : public SimObject
virtual bool useOccupancy() const { return false; }
+ void setCache(CacheMemory * pCache) {m_cache = pCache;}
+ CacheMemory * m_cache;
+
protected:
unsigned m_num_sets; /** total number of sets */
unsigned m_assoc; /** set associativity */
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index d08724cff..e444ae09c 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -63,6 +63,7 @@ CacheMemory::CacheMemory(const Params *p)
m_latency = p->latency;
m_cache_assoc = p->assoc;
m_replacementPolicy_ptr = p->replacement_policy;
+ m_replacementPolicy_ptr->setCache(this);
m_start_index_bit = p->start_index_bit;
m_is_instruction_only_cache = p->is_icache;
m_resource_stalls = p->resourceStalls;
@@ -592,3 +593,15 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr)
return true;
}
}
+
+bool
+CacheMemory::isBlockInvalid(int64 cache_set, int64 loc)
+{
+ return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid);
+}
+
+bool
+CacheMemory::isBlockNotBusy(int64 cache_set, int64 loc)
+{
+ return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy);
+}
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index af5e680d8..57f2885b6 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -100,6 +100,8 @@ class CacheMemory : public SimObject
Cycles getTagLatency() const { return tagArray.getLatency(); }
Cycles getDataLatency() const { return dataArray.getLatency(); }
+ bool isBlockInvalid(int64 cache_set, int64 loc);
+ bool isBlockNotBusy(int64 cache_set, int64 loc);
// Hook for checkpointing the contents of the cache
void recordCacheContents(int cntrl, CacheRecorder* tr) const;