diff options
author | Derek Hower <drh5@cs.wisc.edu> | 2009-09-01 09:36:53 -0500 |
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committer | Derek Hower <drh5@cs.wisc.edu> | 2009-09-01 09:36:53 -0500 |
commit | edd522b30a12613946573c0e6c91659949a1f64d (patch) | |
tree | ae399988bb6554a6d3754a7b2e49c8ba4b7d8cd6 /src/mem/ruby | |
parent | 041a8cefc72dd20d99acdd9e1042949f49ab460c (diff) | |
parent | 849bad7ad7c8b483d02b317e7f6ecf0c1292a48d (diff) | |
download | gem5-edd522b30a12613946573c0e6c91659949a1f64d.tar.xz |
Automated merge with ssh://hg@m5sim.org/m5
Diffstat (limited to 'src/mem/ruby')
-rw-r--r-- | src/mem/ruby/config/MI_example-homogeneous.rb | 7 | ||||
-rw-r--r-- | src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb | 7 | ||||
-rw-r--r-- | src/mem/ruby/config/cfg.rb | 2 | ||||
-rw-r--r-- | src/mem/ruby/libruby.cc | 4 | ||||
-rw-r--r-- | src/mem/ruby/libruby.hh | 8 | ||||
-rw-r--r-- | src/mem/ruby/system/CacheMemory.hh | 18 | ||||
-rw-r--r-- | src/mem/ruby/system/DMASequencer.hh | 1 | ||||
-rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 2 | ||||
-rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 55 | ||||
-rw-r--r-- | src/mem/ruby/system/Sequencer.hh | 4 |
10 files changed, 85 insertions, 23 deletions
diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb index 2b416e647..409d0fe3a 100644 --- a/src/mem/ruby/config/MI_example-homogeneous.rb +++ b/src/mem/ruby/config/MI_example-homogeneous.rb @@ -34,6 +34,13 @@ for i in 0..$*.size-1 do elsif $*[i] == "-m" num_memories = $*[i+1].to_i i = i+1 + elsif $*[i] == "-R" + if $*[i+1] == "rand" + RubySystem.random_seed = "rand" + else + RubySystem.random_seed = $*[i+1].to_i + end + i = i+ 1 elsif $*[i] == "-s" memory_size_mb = $*[i+1].to_i i = i + 1 diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb index 8a202d450..2c59a0916 100644 --- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb +++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb @@ -40,6 +40,13 @@ for i in 0..$*.size-1 do elsif $*[i] == "-p" num_cores = $*[i+1].to_i i = i+1 + elsif $*[i] == "-R" + if $*[i+1] == "rand" + RubySystem.random_seed = "rand" + else + RubySystem.random_seed = $*[i+1].to_i + end + i = i+ 1 elsif $*[i] == "-s" memory_size_mb = $*[i+1].to_i i = i + 1 diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb index 445bb4885..16d658a4c 100644 --- a/src/mem/ruby/config/cfg.rb +++ b/src/mem/ruby/config/cfg.rb @@ -11,7 +11,7 @@ end def assert(condition,message) unless condition - raise AssertionFailure, "\n\nAssertion failed: \n\n #{message}\n\n" + raise AssertionFailure.new(message), "\n\nAssertion failed: \n\n #{message}\n\n" end end diff --git a/src/mem/ruby/libruby.cc b/src/mem/ruby/libruby.cc index e4e302eba..71f7e383e 100644 --- a/src/mem/ruby/libruby.cc +++ b/src/mem/ruby/libruby.cc @@ -133,6 +133,10 @@ void libruby_read_ram(uint64_t paddr, uint8_t* data, int len) RubySystem::getMemoryVector()->read(Address(paddr), data, len); } +bool libruby_isReady(RubyPortHandle p, struct RubyRequest request) { + return static_cast<RubyPort*>(p)->isReady(request, true); +} + int64_t libruby_issue_request(RubyPortHandle p, struct RubyRequest request) { return static_cast<RubyPort*>(p)->makeRequest(request); diff --git a/src/mem/ruby/libruby.hh b/src/mem/ruby/libruby.hh index a73ff5cf4..a5418d9e6 100644 --- a/src/mem/ruby/libruby.hh +++ b/src/mem/ruby/libruby.hh @@ -34,7 +34,7 @@ struct RubyRequest { unsigned proc_id; RubyRequest() {} - RubyRequest(uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, unsigned _proc_id = 0) + RubyRequest(uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, unsigned _proc_id = 100) : paddr(_paddr), data(_data), len(_len), pc(_pc), type(_type), access_mode(_access_mode), proc_id(_proc_id) {} }; @@ -76,6 +76,12 @@ RubyPortHandle libruby_get_port_by_name(const char* name); */ int64_t libruby_issue_request(RubyPortHandle p, struct RubyRequest request); + +/** + * + */ +bool libruby_isReady(RubyPortHandle p, struct RubyRequest request); + /** * writes data directly into Ruby's data array. Note that this * ignores caches, and should be considered incoherent after diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index 7a46bd3a5..4b2bc7084 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -156,6 +156,7 @@ private: // The first index is the # of cache lines. // The second index is the the amount associativity. + m5::hash_map<Address, int> m_tag_index; Vector<Vector<AbstractCacheEntry*> > m_cache; Vector<Vector<int> > m_locked; @@ -286,6 +287,12 @@ int CacheMemory::findTagInSet(Index cacheSet, const Address& tag) const { assert(tag == line_address(tag)); // search the set for the tags + m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag); + if (it != m_tag_index.end()) + if (m_cache[cacheSet][it->second]->m_Permission != AccessPermission_NotPresent) + return it->second; + return -1; // Not found + /* for (int i=0; i < m_cache_assoc; i++) { if ((m_cache[cacheSet][i] != NULL) && (m_cache[cacheSet][i]->m_Address == tag) && @@ -294,6 +301,7 @@ int CacheMemory::findTagInSet(Index cacheSet, const Address& tag) const } } return -1; // Not found + */ } // Given a cache index: returns the index of the tag in a set. @@ -303,11 +311,19 @@ int CacheMemory::findTagInSetIgnorePermissions(Index cacheSet, const Address& ta { assert(tag == line_address(tag)); // search the set for the tags + m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag); + if (it != m_tag_index.end()) + return it->second; + return -1; // Not found + /* + assert(tag == line_address(tag)); + // search the set for the tags for (int i=0; i < m_cache_assoc; i++) { if (m_cache[cacheSet][i] != NULL && m_cache[cacheSet][i]->m_Address == tag) return i; } return -1; // Not found + */ } // PUBLIC METHODS @@ -418,6 +434,7 @@ void CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry) m_cache[cacheSet][i]->m_Address = address; m_cache[cacheSet][i]->m_Permission = AccessPermission_Invalid; m_locked[cacheSet][i] = -1; + m_tag_index[address] = i; m_replacementPolicy_ptr->touch(cacheSet, i, g_eventQueue_ptr->getTime()); @@ -439,6 +456,7 @@ void CacheMemory::deallocate(const Address& address) delete m_cache[cacheSet][location]; m_cache[cacheSet][location] = NULL; m_locked[cacheSet][location] = -1; + m_tag_index.erase(address); } } diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh index 1f60b95ec..77c0a2258 100644 --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -25,6 +25,7 @@ public: void init(const vector<string> & argv); /* external interface */ int64_t makeRequest(const RubyRequest & request); + bool isReady(const RubyRequest & request, bool dont_set = false) { assert(0); return false;}; // void issueRequest(uint64_t paddr, uint8* data, int len, bool rw); bool busy() { return m_is_busy;} diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 2f391070f..cc7fd8d1f 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -21,6 +21,8 @@ public: virtual int64_t makeRequest(const RubyRequest & request) = 0; + virtual bool isReady(const RubyRequest & request, bool dont_set = false) = 0; + void registerHitCallback(void (*hit_callback)(int64_t request_id)) { assert(m_hit_callback == NULL); // can't assign hit_callback twice m_hit_callback = hit_callback; diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 780c1128e..9549cc340 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -61,7 +61,7 @@ void Sequencer::init(const vector<string> & argv) m_instCache_ptr = NULL; m_dataCache_ptr = NULL; m_controller = NULL; - m_servicing_atomic = -1; + m_servicing_atomic = 200; m_atomics_counter = 0; for (size_t i=0; i<argv.size(); i+=2) { if ( argv[i] == "controller") { @@ -108,6 +108,7 @@ void Sequencer::wakeup() { WARN_MSG("Possible Deadlock detected"); WARN_EXPR(request); WARN_EXPR(m_version); + WARN_EXPR(request->ruby_request.paddr); WARN_EXPR(keys.size()); WARN_EXPR(current_time); WARN_EXPR(request->issue_time); @@ -344,13 +345,22 @@ void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) { data.setData(ruby_request.data, request_address.getOffset(), ruby_request.len); } } - + if (type == RubyRequestType_RMW_Write) { + if (m_servicing_atomic != ruby_request.proc_id) { + assert(0); + } + assert(m_atomics_counter > 0); + m_atomics_counter--; + if (m_atomics_counter == 0) { + m_servicing_atomic = 200; + } + } m_hit_callback(srequest->id); delete srequest; } // Returns true if the sequencer already has a load or store outstanding -bool Sequencer::isReady(const RubyRequest& request) { +bool Sequencer::isReady(const RubyRequest& request, bool dont_set) { // POLINA: check if we are currently flushing the write buffer, if so Ruby is returned as not ready // to simulate stalling of the front-end // Do we stall all the sequencers? If it is atomic instruction - yes! @@ -365,27 +375,30 @@ bool Sequencer::isReady(const RubyRequest& request) { return false; } - if (m_servicing_atomic != -1 && m_servicing_atomic != (int)request.proc_id) { + assert(request.proc_id != 100); + if (m_servicing_atomic != 200 && m_servicing_atomic != request.proc_id) { assert(m_atomics_counter > 0); return false; } else { - if (request.type == RubyRequestType_RMW_Read) { - if (m_servicing_atomic == -1) { - assert(m_atomics_counter == 0); - m_servicing_atomic = (int)request.proc_id; + if (!dont_set) { + if (request.type == RubyRequestType_RMW_Read) { + if (m_servicing_atomic == 200) { + assert(m_atomics_counter == 0); + m_servicing_atomic = request.proc_id; + } + else { + assert(m_servicing_atomic == request.proc_id); + } + m_atomics_counter++; } else { - assert(m_servicing_atomic == (int)request.proc_id); - } - m_atomics_counter++; - } - else if (request.type == RubyRequestType_RMW_Write) { - assert(m_servicing_atomic == (int)request.proc_id); - assert(m_atomics_counter > 0); - m_atomics_counter--; - if (m_atomics_counter == 0) { - m_servicing_atomic = -1; + if (m_servicing_atomic == request.proc_id) { + if (request.type != RubyRequestType_RMW_Write) { + m_servicing_atomic = 200; + m_atomics_counter = 0; + } + } } } } @@ -405,7 +418,7 @@ int64_t Sequencer::makeRequest(const RubyRequest & request) int64_t id = makeUniqueRequestID(); SequencerRequest *srequest = new SequencerRequest(request, id, g_eventQueue_ptr->getTime()); bool found = insertRequest(srequest); - if (!found) + if (!found) { if (request.type == RubyRequestType_Locked_Write) { // NOTE: it is OK to check the locked flag here as the mandatory queue will be checked first // ensuring that nothing comes between checking the flag and servicing the store @@ -423,6 +436,10 @@ int64_t Sequencer::makeRequest(const RubyRequest & request) // TODO: issue hardware prefetches here return id; + } + else { + assert(0); + } } else { return -1; diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 2b1f023c5..e75cdaa3a 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -84,7 +84,7 @@ public: // called by Tester or Simics int64_t makeRequest(const RubyRequest & request); - bool isReady(const RubyRequest& request); + bool isReady(const RubyRequest& request, bool dont_set = false); bool empty() const; void print(ostream& out) const; @@ -125,7 +125,7 @@ private: // Global outstanding request count, across all request tables int m_outstanding_count; bool m_deadlock_check_scheduled; - int m_servicing_atomic; + unsigned m_servicing_atomic; int m_atomics_counter; }; |