diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:21 -0800 |
---|---|---|
committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:21 -0800 |
commit | ce2d13195ba14766e7ac7f093b369865b6c92cac (patch) | |
tree | c7525d386d03560399a1499e8704734066843685 /src/mem/ruby | |
parent | dc758641c938bb3941bfc1751dc8c3781d99b441 (diff) | |
download | gem5-ce2d13195ba14766e7ac7f093b369865b6c92cac.tar.xz |
ruby: FS support using the new configuration system
Diffstat (limited to 'src/mem/ruby')
-rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 55 | ||||
-rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 6 | ||||
-rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 2 | ||||
-rw-r--r-- | src/mem/ruby/system/Sequencer.py | 3 |
4 files changed, 31 insertions, 35 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index d8fb6b470..692c9ea81 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -36,12 +36,13 @@ uint16_t RubyPort::m_num_ports = 0; RubyPort::RequestMap RubyPort::pending_cpu_requests; RubyPort::RubyPort(const Params *p) - : MemObject(p), - funcMemPort(csprintf("%s-funcmem_port", name()), this) + : MemObject(p) { m_version = p->version; assert(m_version != -1); + physmem = p->physmem; + m_controller = NULL; m_mandatory_q_ptr = NULL; @@ -49,6 +50,7 @@ RubyPort::RubyPort(const Params *p) m_request_cnt = 0; m_hit_callback = ruby_hit_callback; pio_port = NULL; + physMemPort = NULL; assert(m_num_ports <= 2048); // see below for reason } @@ -73,8 +75,23 @@ RubyPort::getPort(const std::string &if_name, int idx) this); return pio_port; - } else if (if_name == "funcmem_port") { - return &funcMemPort; + } else if (if_name == "physMemPort") { + // + // RubyPort should only have one port to physical memory + // + assert (physMemPort == NULL); + + physMemPort = new M5Port(csprintf("%s-physMemPort", name()), + this); + + return physMemPort; + } else if (if_name == "functional") { + // + // Calls for the functional port only want to access functional memory. + // Therefore, directly pass these calls ports to physmem. + // + assert(physmem != NULL); + return physmem->getPort(if_name, idx); } return NULL; } @@ -248,11 +265,11 @@ RubyPort::M5Port::hitCallback(PacketPtr pkt) DPRINTF(MemoryAccess, "Hit callback needs response %d\n", needsResponse); - ruby_port->funcMemPort.sendFunctional(pkt); + ruby_port->physMemPort->sendAtomic(pkt); // turn packet around to go back to requester if response expected if (needsResponse) { - // recvAtomic() should already have turned packet into + // sendAtomic() should already have turned packet into // atomic response assert(pkt->isResponse()); DPRINTF(MemoryAccess, "Sending packet back over port\n"); @@ -282,7 +299,7 @@ RubyPort::M5Port::isPhysMemAddress(Addr addr) { AddrRangeList physMemAddrList; bool snoop = false; - ruby_port->funcMemPort.getPeerAddressRanges(physMemAddrList, snoop); + ruby_port->physMemPort->getPeerAddressRanges(physMemAddrList, snoop); for(AddrRangeIter iter = physMemAddrList.begin(); iter != physMemAddrList.end(); iter++) { @@ -292,29 +309,5 @@ RubyPort::M5Port::isPhysMemAddress(Addr addr) return true; } } - assert(isPioAddress(addr)); return false; } - -bool -RubyPort::M5Port::isPioAddress(Addr addr) -{ - AddrRangeList pioAddrList; - bool snoop = false; - if (ruby_port->pio_port == NULL) { - return false; - } - - ruby_port->pio_port->getPeerAddressRanges(pioAddrList, snoop); - for(AddrRangeIter iter = pioAddrList.begin(); - iter != pioAddrList.end(); - iter++) { - if (addr >= iter->start && addr <= iter->end) { - DPRINTF(MemoryAccess, "Pio request found in %#llx - %#llx range\n", - iter->start, iter->end); - return true; - } - } - return false; -} - diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index a03c4dce2..e57f663c9 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -36,6 +36,7 @@ #include "mem/mem_object.hh" #include "mem/tport.hh" +#include "mem/physical.hh" #include "params/RubyPort.hh" @@ -63,7 +64,6 @@ public: virtual Tick recvAtomic(PacketPtr pkt); private: - bool isPioAddress(Addr addr); bool isPhysMemAddress(Addr addr); }; @@ -169,7 +169,9 @@ private: static RequestMap pending_cpu_requests; static void ruby_hit_callback(int64_t req_id); - FunctionalPort funcMemPort; + M5Port* physMemPort; + + PhysicalMemory* physmem; }; #endif diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 23a6b44e2..00ae5364c 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -197,7 +197,7 @@ bool Sequencer::insertRequest(SequencerRequest* request) { // See if we should schedule a deadlock check if (deadlockCheckEvent.scheduled() == false) { - schedule(deadlockCheckEvent, m_deadlock_threshold); + schedule(deadlockCheckEvent, m_deadlock_threshold + curTick); } Address line_addr(request->ruby_request.paddr); diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 1333204a2..30cb9add0 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -8,6 +8,8 @@ class RubyPort(MemObject): port = VectorPort("M5 port") version = Param.Int(0, "") pio_port = Port("Ruby_pio_port") + physmem = Param.PhysicalMemory("") + physMemPort = Port("port to physical memory") class RubySequencer(RubyPort): type = 'RubySequencer' @@ -18,7 +20,6 @@ class RubySequencer(RubyPort): "max requests (incl. prefetches) outstanding") deadlock_threshold = Param.Int(500000, "max outstanding cycles for a request before deadlock/livelock declared") - funcmem_port = Port("port to functional memory") class DMASequencer(RubyPort): type = 'DMASequencer' |