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author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-27 09:08:29 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-27 09:08:29 -0400 |
commit | de62aedabc96e7492c40bbc4468ba42b3274bfd6 (patch) | |
tree | e68dae6dd1f3da0e7d2dcf3e946728c46e63bbce /src/mem/ruby | |
parent | 71d5f03175b3a684b94bbc515ebc02e2b493b7cf (diff) | |
download | gem5-de62aedabc96e7492c40bbc4468ba42b3274bfd6.tar.xz |
misc: Fix a bunch of minor issues identified by static analysis
Add some missing initialisation, and fix a handful benign resource
leaks (including some false positives).
Diffstat (limited to 'src/mem/ruby')
-rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 110b6924d..71b08ebbb 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -205,7 +205,11 @@ RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); for (auto it = l.begin(); it != l.end(); ++it) { if (it->contains(pkt->getAddr())) { - ruby_port->master_ports[i]->sendTimingReq(pkt); + // generally it is not safe to assume success here as + // the port could be blocked + bool M5_VAR_USED success = + ruby_port->master_ports[i]->sendTimingReq(pkt); + assert(success); return true; } } |