ruby: Reincarnated the responding machine profiling

This patch adds back to ruby the capability to understand the response time
for messages that hit in different levels of the cache heirarchy.
Specifically add support for the MI_example, MOESI_hammer, and MOESI_CMP_token
protocols.

4 files changed, 57 insertions, 17 deletions

diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index 2b844ef9d..753fdd230 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -574,23 +574,27 @@ Profiler::bankBusy()
 
 // non-zero cycle demand request
 void
-Profiler::missLatency(Time t, RubyRequestType type)
+Profiler::missLatency(Time cycles, 
+                      RubyRequestType type,
+                      const GenericMachineType respondingMach)
 {
-    m_allMissLatencyHistogram.add(t);
-    m_missLatencyHistograms[type].add(t);
+    m_allMissLatencyHistogram.add(cycles);
+    m_missLatencyHistograms[type].add(cycles);
+    m_machLatencyHistograms[respondingMach].add(cycles);
 }
 
 // non-zero cycle prefetch request
 void
-Profiler::swPrefetchLatency(Time t, CacheRequestType type,
-                            GenericMachineType respondingMach)
+Profiler::swPrefetchLatency(Time cycles, 
+                            CacheRequestType type,
+                            const GenericMachineType respondingMach)
 {
-    m_allSWPrefetchLatencyHistogram.add(t);
-    m_SWPrefetchLatencyHistograms[type].add(t);
-    m_SWPrefetchMachLatencyHistograms[respondingMach].add(t);
+    m_allSWPrefetchLatencyHistogram.add(cycles);
+    m_SWPrefetchLatencyHistograms[type].add(cycles);
+    m_SWPrefetchMachLatencyHistograms[respondingMach].add(cycles);
     if (respondingMach == GenericMachineType_Directory ||
         respondingMach == GenericMachineType_NUM) {
-        m_SWPrefetchL2MissLatencyHistogram.add(t);
+        m_SWPrefetchL2MissLatencyHistogram.add(cycles);
     }
 }
 
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index 20491cab7..de9834f05 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -133,9 +133,15 @@ class Profiler : public SimObject, public Consumer
 
     void controllerBusy(MachineID machID);
     void bankBusy();
-    void missLatency(Time t, RubyRequestType type);
-    void swPrefetchLatency(Time t, CacheRequestType type,
-                           GenericMachineType respondingMach);
+
+    void missLatency(Time t, 
+                     RubyRequestType type,
+                     const GenericMachineType respondingMach);
+
+    void swPrefetchLatency(Time t, 
+                           CacheRequestType type,
+                           const GenericMachineType respondingMach);
+
     void sequencerRequests(int num) { m_sequencer_requests.add(num); }
 
     void profileTransition(const std::string& component, NodeID version,
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 19bcb4b1c..e4f85908f 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -305,6 +305,14 @@ Sequencer::removeRequest(SequencerRequest* srequest)
 void
 Sequencer::writeCallback(const Address& address, DataBlock& data)
 {
+    writeCallback(address, GenericMachineType_NULL, data);
+}
+
+void
+Sequencer::writeCallback(const Address& address,
+                         GenericMachineType mach, 
+                         DataBlock& data)
+{
     assert(address == line_address(address));
     assert(m_writeRequestTable.count(line_address(address)));
 
@@ -329,12 +337,20 @@ Sequencer::writeCallback(const Address& address, DataBlock& data)
         m_controller->unblock(address);
     }
 
-    hitCallback(request, data);
+    hitCallback(request, mach, data);
 }
 
 void
 Sequencer::readCallback(const Address& address, DataBlock& data)
 {
+    readCallback(address, GenericMachineType_NULL, data);
+}
+
+void
+Sequencer::readCallback(const Address& address,
+                        GenericMachineType mach,
+                        DataBlock& data)
+{
     assert(address == line_address(address));
     assert(m_readRequestTable.count(line_address(address)));
 
@@ -349,11 +365,13 @@ Sequencer::readCallback(const Address& address, DataBlock& data)
            (request->ruby_request.type == RubyRequestType_RMW_Read) ||
            (request->ruby_request.type == RubyRequestType_IFETCH));
 
-    hitCallback(request, data);
+    hitCallback(request, mach, data);
 }
 
 void
-Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data)
+Sequencer::hitCallback(SequencerRequest* srequest,
+                       GenericMachineType mach,
+                       DataBlock& data)
 {
     const RubyRequest & ruby_request = srequest->ruby_request;
     Address request_address(ruby_request.paddr);
@@ -376,7 +394,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data)
 
     // Profile the miss latency for all non-zero demand misses
     if (miss_latency != 0) {
-        g_system_ptr->getProfiler()->missLatency(miss_latency, type);
+        g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
 
         if (Debug::getProtocolTrace()) {
             g_system_ptr->getProfiler()->
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index a336751fd..fd6b390c2 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -75,8 +75,17 @@ class Sequencer : public RubyPort, public Consumer
     void printProgress(std::ostream& out) const;
 
     void writeCallback(const Address& address, DataBlock& data);
+
+    void writeCallback(const Address& address, 
+                       GenericMachineType mach, 
+                       DataBlock& data);
+
     void readCallback(const Address& address, DataBlock& data);
 
+    void readCallback(const Address& address, 
+                      GenericMachineType mach, 
+                      DataBlock& data);
+
     RequestStatus makeRequest(const RubyRequest & request);
     RequestStatus getRequestStatus(const RubyRequest& request);
     bool empty() const;
@@ -94,7 +103,10 @@ class Sequencer : public RubyPort, public Consumer
                         int size, DataBlock*& data_ptr);
     void issueRequest(const RubyRequest& request);
 
-    void hitCallback(SequencerRequest* request, DataBlock& data);
+    void hitCallback(SequencerRequest* request, 
+                     GenericMachineType mach,
+                     DataBlock& data);
+
     bool insertRequest(SequencerRequest* request);