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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2009-11-18 13:55:58 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2009-11-18 13:55:58 -0800 |
| commit | 90d6e2652fc8590116d436a1143700e11893cfa4 (patch) | |
| tree | 47b58a565a62897fd9fd0d4184409ad1f4c0f713 /src/mem/rubymem.hh | |
| parent | dce53610c374eba2a8dae236a13b3197cd42edc6 (diff) | |
| download | gem5-90d6e2652fc8590116d436a1143700e11893cfa4.tar.xz | |
ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of ports
per core. CPUs have two ports: icache + dcache. MemTester has one port.
Diffstat (limited to 'src/mem/rubymem.hh')
| -rw-r--r-- | src/mem/rubymem.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/rubymem.hh b/src/mem/rubymem.hh index dd0a492f5..2672dcb77 100644 --- a/src/mem/rubymem.hh +++ b/src/mem/rubymem.hh @@ -130,6 +130,7 @@ class RubyMemory : public PhysicalMemory Tick ruby_clock; Tick ruby_phase; RubyExitCallback* rubyExitCB; + int ports_per_cpu; public: static std::map<int64_t, PacketPtr> pending_requests; |