arch, mem, sim: Consolidate and rename the SE mode page table classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/mem/se_translating_port_proxy.hh b/src/mem/se_translating_port_proxy.hh
index 5ac6b5286..2f2a81b59 100644
--- a/src/mem/se_translating_port_proxy.hh
+++ b/src/mem/se_translating_port_proxy.hh
@@ -47,7 +47,7 @@
 
 #include "mem/port_proxy.hh"
 
-class PageTableBase;
+class EmulationPageTable;
 class Process;
 
 /**
@@ -75,7 +75,7 @@ class SETranslatingPortProxy : public PortProxy
     };
 
   private:
-    PageTableBase *pTable;
+    EmulationPageTable *pTable;
     Process *process;
     AllocType allocating;
 
@@ -83,7 +83,7 @@ class SETranslatingPortProxy : public PortProxy
     SETranslatingPortProxy(MasterPort& port, Process* p, AllocType alloc);
     virtual ~SETranslatingPortProxy();
 
-    void setPageTable(PageTableBase *p) { pTable = p; }
+    void setPageTable(EmulationPageTable *p) { pTable = p; }
     void setProcess(Process *p) { process = p; }
     bool tryReadBlob(Addr addr, uint8_t *p, int size) const;
     bool tryWriteBlob(Addr addr, const uint8_t *p, int size) const;