mem: Add bytes per activate DRAM controller stat

This patch adds a histogram to track how many bytes are accessed in an
open row before it is closed. This metric is useful in characterising
a workload and the efficiency of the DRAM scheduler. For example, a
DDR3-1600 device requires 44 cycles (tRC) before it can activate
another row in the same bank. For a x32 interface (8 bytes per cycle)
that means 8 x 44 = 352 bytes must be transferred to hide the
preparation time.

1 files changed, 9 insertions, 4 deletions

diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh
index 920dcf33a..e4d20163a 100644
--- a/src/mem/simple_dram.hh
+++ b/src/mem/simple_dram.hh
@@ -133,8 +133,10 @@ class SimpleDRAM : public AbstractMemory
     std::deque<Tick> actTicks;
 
     /**
-     * A basic class to track the bank state indirectly via
-     * times "freeAt" and "tRASDoneAt" and what page is currently open
+     * A basic class to track the bank state indirectly via times
+     * "freeAt" and "tRASDoneAt" and what page is currently open. The
+     * bank also keeps track of how many bytes have been accessed in
+     * the open row since it was opened.
      */
     class Bank
     {
@@ -148,7 +150,10 @@ class SimpleDRAM : public AbstractMemory
         Tick freeAt;
         Tick tRASDoneAt;
 
-        Bank() : openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0)
+        uint32_t bytesAccessed;
+
+        Bank() :
+            openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0), bytesAccessed(0)
         { }
     };
 
@@ -452,7 +457,7 @@ class SimpleDRAM : public AbstractMemory
     Stats::Vector writePktSize;
     Stats::Vector rdQLenPdf;
     Stats::Vector wrQLenPdf;
-
+    Stats::Histogram bytesPerActivate;
 
     // Latencies summed over all requests
     Stats::Scalar totQLat;