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authorAli Saidi <Ali.Saidi@ARM.com>2012-11-02 11:50:16 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2012-11-02 11:50:16 -0500
commitce5766c409ca3e27e62a300b89511b9d0fcd6c18 (patch)
tree32ef02e398c9edec9ee0acb926d6fd925b3d069f /src/mem/simple_dram.hh
parent1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (diff)
downloadgem5-ce5766c409ca3e27e62a300b89511b9d0fcd6c18.tar.xz
mem: fix use after free issue in memories until 4-phase work complete.
Diffstat (limited to 'src/mem/simple_dram.hh')
-rw-r--r--src/mem/simple_dram.hh6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh
index 373408c2a..de597d668 100644
--- a/src/mem/simple_dram.hh
+++ b/src/mem/simple_dram.hh
@@ -453,6 +453,12 @@ class SimpleDRAM : public AbstractMemory
Stats::Formula writeRowHitRate;
Stats::Formula avgGap;
+ /** @todo this is a temporary workaround until the 4-phase code is
+ * committed. upstream caches needs this packet until true is returned, so
+ * hold onto it for deletion until a subsequent call
+ */
+ std::vector<PacketPtr> pendingDelete;
+
public:
void regStats();