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authorAndreas Hansson <andreas.hansson@arm.com>2014-03-23 11:12:03 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-03-23 11:12:03 -0400
commit116985d661f6383bf2b61fa9b9d3df96e52fdb6d (patch)
treeb4442e976e3ab715c51ec4560a2a72959a91c385 /src/mem/simple_dram.hh
parent6557741311f28f718cc33f9abde36d7e51f3585c (diff)
downloadgem5-116985d661f6383bf2b61fa9b9d3df96e52fdb6d.tar.xz
mem: Limit the accesses to a page before forcing a precharge
This patch adds a basic starvation-prevention mechanism where a DRAM page is forced to close after a certain number of accesses. The limit is combined with the open and open-adaptive page policy and if reached causes an auto-precharge.
Diffstat (limited to 'src/mem/simple_dram.hh')
-rw-r--r--src/mem/simple_dram.hh9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh
index 8ecce94b7..7f58843aa 100644
--- a/src/mem/simple_dram.hh
+++ b/src/mem/simple_dram.hh
@@ -155,11 +155,12 @@ class SimpleDRAM : public AbstractMemory
Tick tRASDoneAt;
Tick actAllowedAt;
+ uint32_t rowAccesses;
uint32_t bytesAccessed;
Bank() :
openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0), actAllowedAt(0),
- bytesAccessed(0)
+ rowAccesses(0), bytesAccessed(0)
{ }
};
@@ -508,6 +509,12 @@ class SimpleDRAM : public AbstractMemory
Enums::PageManage pageMgmt;
/**
+ * Max column accesses (read and write) per row, before forefully
+ * closing it.
+ */
+ const uint32_t maxAccessesPerRow;
+
+ /**
* Pipeline latency of the controller frontend. The frontend
* contribution is added to writes (that complete when they are in
* the write buffer) and reads that are serviced the write buffer.