mem: Add tRAS parameter to the DRAM controller model

This patch adds an explicit tRAS parameter to the DRAM controller
model. Previously tRAS was, rather conservatively, assumed to be tRCD
+ tCL + tRP. The default values for tRAS are chosen to match the
previous behaviour and will be updated later.

1 files changed, 1 insertions, 0 deletions

diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh
index abc64c3cd..a340a427d 100644
--- a/src/mem/simple_dram.hh
+++ b/src/mem/simple_dram.hh
@@ -462,6 +462,7 @@ class SimpleDRAM : public AbstractMemory
     const Tick tRCD;
     const Tick tCL;
     const Tick tRP;
+    const Tick tRAS;
     const Tick tRFC;
     const Tick tREFI;
     const Tick tXAW;