mem: Just-in-time write scheduling in DRAM controller

This patch removes the untimed while loop in the write scheduling
mechanism and now schedule commands taking into account the minimum
timing constraint. It also introduces an optimization to track write
queue size and switch from writes to reads if the number of write
requests fall below write low threshold.

1 files changed, 13 insertions, 2 deletions

diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh
index dfb8fc15f..a7a100d7c 100644
--- a/src/mem/simple_dram.hh
+++ b/src/mem/simple_dram.hh
@@ -472,8 +472,10 @@ class SimpleDRAM : public AbstractMemory
     uint32_t columnsPerRowBuffer;
     const uint32_t readBufferSize;
     const uint32_t writeBufferSize;
-    const double writeThresholdPerc;
-    uint32_t writeThreshold;
+    const double writeHighThresholdPerc;
+    uint32_t writeHighThreshold;
+    const double writeLowThresholdPerc;
+    uint32_t writeLowThreshold;
 
     /**
      * Basic memory timing parameters initialized based on parameter
@@ -522,6 +524,15 @@ class SimpleDRAM : public AbstractMemory
     Tick prevArrival;
     int numReqs;
 
+    // Tracks number of writes done to meet the write threshold
+    uint32_t numWritesThisTime;
+
+    // The absolute soonest you have to start thinking about the
+    // next request is the longest access time that can occur before
+    // busBusyUntil. Assuming you need to precharge,
+    // open a new row, and access, it is tRP + tRCD + tCL
+    Tick newTime;
+
     // All statistics that the model needs to capture
     Stats::Scalar readReqs;
     Stats::Scalar writeReqs;