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authorAni Udipi <ani.udipi@arm.com>2013-11-01 11:56:19 -0400
committerAni Udipi <ani.udipi@arm.com>2013-11-01 11:56:19 -0400
commitea76f9757668018ad1f2ccb50fd61b9288057913 (patch)
treec48c3c071c6cd41ba1a2d81e21b4e1fa79fbfa92 /src/mem/simple_dram.hh
parent655bf868282ac2d9d6a711167efa936e7057d405 (diff)
downloadgem5-ea76f9757668018ad1f2ccb50fd61b9288057913.tar.xz
mem: Use the same timing calculation for DRAM read and write
This patch simplifies the DRAM model by re-using the function that computes the busy and access time for both reads and writes.
Diffstat (limited to 'src/mem/simple_dram.hh')
-rw-r--r--src/mem/simple_dram.hh11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh
index a340a427d..edba58774 100644
--- a/src/mem/simple_dram.hh
+++ b/src/mem/simple_dram.hh
@@ -198,6 +198,8 @@ class SimpleDRAM : public AbstractMemory
/** This comes from the outside world */
const PacketPtr pkt;
+ const bool isRead;
+
/** Will be populated by address decoder */
const uint8_t rank;
const uint16_t bank;
@@ -224,12 +226,12 @@ class SimpleDRAM : public AbstractMemory
BurstHelper* burstHelper;
Bank& bank_ref;
- DRAMPacket(PacketPtr _pkt, uint8_t _rank, uint16_t _bank,
+ DRAMPacket(PacketPtr _pkt, bool _isRead, uint8_t _rank, uint16_t _bank,
uint16_t _row, Addr _addr, unsigned int _size,
Bank& _bank_ref)
: entryTime(curTick()), readyTime(curTick()),
- pkt(_pkt), rank(_rank), bank(_bank), row(_row), addr(_addr),
- size(_size), burstHelper(NULL), bank_ref(_bank_ref)
+ pkt(_pkt), isRead(_isRead), rank(_rank), bank(_bank), row(_row),
+ addr(_addr), size(_size), burstHelper(NULL), bank_ref(_bank_ref)
{ }
};
@@ -336,9 +338,10 @@ class SimpleDRAM : public AbstractMemory
* @param pkt The packet from the outside world
* @param dramPktAddr The starting address of the DRAM packet
* @param size The size of the DRAM packet in bytes
+ * @param isRead Is the request for a read or a write to DRAM
* @return A DRAMPacket pointer with the decoded information
*/
- DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size);
+ DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, bool isRead);
/**
* The memory schduler/arbiter - picks which read request needs to