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authorAndreas Hansson <andreas.hansson@arm.com>2014-03-23 11:12:01 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-03-23 11:12:01 -0400
commit6557741311f28f718cc33f9abde36d7e51f3585c (patch)
treef5d77bce64a777801d40ef9901cff9b1c17c69c8 /src/mem/simple_dram.hh
parent7d883df7e58b6e61ed93717f6fde251086d50153 (diff)
downloadgem5-6557741311f28f718cc33f9abde36d7e51f3585c.tar.xz
mem: Make DRAM write queue draining more aggressive
This patch changes the triggering condition for the write draining such that we grab the opportunity to issue writes if there are no reads waiting (as opposed to waiting for the writes to reach the high threshold). As a result, we potentially drain some of the writes in read idle periods (if any). A low threshold is added to be able to control how many write bursts are kept in the memory controller queue (acting as on-chip storage). The high and low thresholds are updated to sensible values for a 32/64 size write buffer. Note that the thresholds should be adjusted along with the queue sizes. This patch also adds some basic initialisation sanity checks and moves part of the initialisation to the constructor.
Diffstat (limited to 'src/mem/simple_dram.hh')
-rw-r--r--src/mem/simple_dram.hh13
1 files changed, 5 insertions, 8 deletions
diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh
index 0731b14bb..8ecce94b7 100644
--- a/src/mem/simple_dram.hh
+++ b/src/mem/simple_dram.hh
@@ -471,17 +471,17 @@ class SimpleDRAM : public AbstractMemory
const uint32_t devicesPerRank;
const uint32_t burstSize;
const uint32_t rowBufferSize;
+ const uint32_t columnsPerRowBuffer;
const uint32_t ranksPerChannel;
const uint32_t banksPerRank;
const uint32_t channels;
uint32_t rowsPerBank;
- uint32_t columnsPerRowBuffer;
const uint32_t readBufferSize;
const uint32_t writeBufferSize;
- const double writeHighThresholdPerc;
- uint32_t writeHighThreshold;
- const double writeLowThresholdPerc;
- uint32_t writeLowThreshold;
+ const uint32_t writeHighThreshold;
+ const uint32_t writeLowThreshold;
+ const uint32_t minWritesPerSwitch;
+ uint32_t writesThisTime;
/**
* Basic memory timing parameters initialized based on parameter
@@ -530,9 +530,6 @@ class SimpleDRAM : public AbstractMemory
Tick prevArrival;
int numReqs;
- // Tracks number of writes done to meet the write threshold
- uint32_t numWritesThisTime;
-
// The absolute soonest you have to start thinking about the
// next request is the longest access time that can occur before
// busBusyUntil. Assuming you need to precharge,