MEM: Enable multiple distributed generalized memories

This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.

--HG--
rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py
rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py
rename : src/mem/physical.cc => src/mem/abstract_mem.cc
rename : src/mem/physical.hh => src/mem/abstract_mem.hh
rename : src/mem/physical.cc => src/mem/simple_mem.cc
rename : src/mem/physical.hh => src/mem/simple_mem.hh

1 files changed, 167 insertions, 0 deletions

diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
new file mode 100644
index 000000000..10e809d0b
--- /dev/null
+++ b/src/mem/simple_mem.cc
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2010-2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ron Dreslinski
+ *          Ali Saidi
+ *          Andreas Hansson
+ */
+
+#include "base/random.hh"
+#include "mem/simple_mem.hh"
+
+using namespace std;
+
+SimpleMemory::SimpleMemory(const Params* p) :
+    AbstractMemory(p),
+    lat(p->latency), lat_var(p->latency_var)
+{
+    for (size_t i = 0; i < p->port_port_connection_count; ++i) {
+        ports.push_back(new MemoryPort(csprintf("%s-port-%d", name(), i),
+                                       *this));
+    }
+}
+
+void
+SimpleMemory::init()
+{
+    for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
+         ++p) {
+        if (!(*p)->isConnected()) {
+            fatal("SimpleMemory port %s is unconnected!\n", (*p)->name());
+        } else {
+            (*p)->sendRangeChange();
+        }
+    }
+}
+
+Tick
+SimpleMemory::calculateLatency(PacketPtr pkt)
+{
+    if (pkt->memInhibitAsserted()) {
+        return 0;
+    } else {
+        Tick latency = lat;
+        if (lat_var != 0)
+            latency += random_mt.random<Tick>(0, lat_var);
+        return latency;
+    }
+}
+
+Tick
+SimpleMemory::doAtomicAccess(PacketPtr pkt)
+{
+    access(pkt);
+    return calculateLatency(pkt);
+}
+
+void
+SimpleMemory::doFunctionalAccess(PacketPtr pkt)
+{
+    functionalAccess(pkt);
+}
+
+SlavePort &
+SimpleMemory::getSlavePort(const std::string &if_name, int idx)
+{
+    if (if_name != "port") {
+        return MemObject::getSlavePort(if_name, idx);
+    } else {
+        if (idx >= static_cast<int>(ports.size())) {
+            fatal("SimpleMemory::getSlavePort: unknown index %d\n", idx);
+        }
+
+        return *ports[idx];
+    }
+}
+
+unsigned int
+SimpleMemory::drain(Event *de)
+{
+    int count = 0;
+    for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
+         ++p) {
+        count += (*p)->drain(de);
+    }
+
+    if (count)
+        changeState(Draining);
+    else
+        changeState(Drained);
+    return count;
+}
+
+SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
+                                     SimpleMemory& _memory)
+    : SimpleTimingPort(_name, &_memory), memory(_memory)
+{ }
+
+AddrRangeList
+SimpleMemory::MemoryPort::getAddrRanges()
+{
+    AddrRangeList ranges;
+    ranges.push_back(memory.getAddrRange());
+    return ranges;
+}
+
+Tick
+SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
+{
+    return memory.doAtomicAccess(pkt);
+}
+
+void
+SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
+{
+    pkt->pushLabel(memory.name());
+
+    if (!queue.checkFunctional(pkt)) {
+        // Default implementation of SimpleTimingPort::recvFunctional()
+        // calls recvAtomic() and throws away the latency; we can save a
+        // little here by just not calculating the latency.
+        memory.doFunctionalAccess(pkt);
+    }
+
+    pkt->popLabel();
+}
+
+SimpleMemory*
+SimpleMemoryParams::create()
+{
+    return new SimpleMemory(this);
+}