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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-12 12:56:13 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-12 12:56:13 -0400 |
commit | f00cba34eb8e6bf947721f72de314f4e8bd6a8f8 (patch) | |
tree | 432ab17d82d72d5042758f25066dc64558c9a7f8 /src/mem/simple_mem.cc | |
parent | 55bfe13705a3eccdffb6846dd87df5f190b04c99 (diff) | |
download | gem5-f00cba34eb8e6bf947721f72de314f4e8bd6a8f8.tar.xz |
Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.
There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
Diffstat (limited to 'src/mem/simple_mem.cc')
-rw-r--r-- | src/mem/simple_mem.cc | 29 |
1 files changed, 7 insertions, 22 deletions
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc index aa9168bf7..b9db64276 100644 --- a/src/mem/simple_mem.cc +++ b/src/mem/simple_mem.cc @@ -49,24 +49,17 @@ using namespace std; SimpleMemory::SimpleMemory(const Params* p) : AbstractMemory(p), - lat(p->latency), lat_var(p->latency_var) + port(name() + ".port", *this), lat(p->latency), lat_var(p->latency_var) { - for (size_t i = 0; i < p->port_port_connection_count; ++i) { - ports.push_back(new MemoryPort(csprintf("%s-port-%d", name(), i), - *this)); - } } void SimpleMemory::init() { - for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end(); - ++p) { - if (!(*p)->isConnected()) { - fatal("SimpleMemory port %s is unconnected!\n", (*p)->name()); - } else { - (*p)->sendRangeChange(); - } + // allow unconnected memories as this is used in several ruby + // systems at the moment + if (port.isConnected()) { + port.sendRangeChange(); } } @@ -102,22 +95,14 @@ SimpleMemory::getSlavePort(const std::string &if_name, int idx) if (if_name != "port") { return MemObject::getSlavePort(if_name, idx); } else { - if (idx >= static_cast<int>(ports.size())) { - fatal("SimpleMemory::getSlavePort: unknown index %d\n", idx); - } - - return *ports[idx]; + return port; } } unsigned int SimpleMemory::drain(Event *de) { - int count = 0; - for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end(); - ++p) { - count += (*p)->drain(de); - } + int count = port.drain(de); if (count) changeState(Draining); |