Mem: Make SimpleMemory single ported

This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.

There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.

1 files changed, 5 insertions, 4 deletions

diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 5f136ed51..95bfa57ad 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -54,9 +54,10 @@
 #include "params/SimpleMemory.hh"
 
 /**
- * The simple memory is a basic multi-ported memory with an infinite
- * throughput and a fixed latency, potentially with a variance added
- * to it. It uses a SimpleTimingPort to implement the timing accesses.
+ * The simple memory is a basic single-ported memory controller with
+ * an infinite throughput and a fixed latency, potentially with a
+ * variance added to it. It uses a SimpleTimingPort to implement the
+ * timing accesses.
  */
 class SimpleMemory : public AbstractMemory
 {
@@ -81,7 +82,7 @@ class SimpleMemory : public AbstractMemory
 
     };
 
-    std::vector<MemoryPort*> ports;
+    MemoryPort port;
 
     Tick lat;
     Tick lat_var;