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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-03 22:44:29 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-03 22:44:29 -0500 |
commit | 676ae5782796bd6b4f202e138b72c1048efceabd (patch) | |
tree | 9fc422b12874e842f4ea4bb473e3c24d8275c6e6 /src/mem/slicc/ast/IfStatementAST.py | |
parent | 9bf3b8828a19570f50914d86d76e32896ecd12bb (diff) | |
download | gem5-676ae5782796bd6b4f202e138b72c1048efceabd.tar.xz |
ruby: mesi three level: multiple corrections to the protocol
1. Eliminate state NP in L0 and L1 Caches: The two states 'NP' and 'I' both
mean that the cache block is not present in the cache. 'I' also means that the
cache entry has been allocated. This causes problems when we do not correctly
initialize the cache entry when it is re-used. Hence, this patch eliminates
the state NP altogether. Everytime a new block comes into the cache, a cache
entry is allocated. Everytime a block leaves, the corresponding entry is
deallocated.
2. Separate transient state for instruction fetches: purely for accouting
purposes.
3. Drop state IS_I in L1 Cache and the message type STALE_DATA: when
invalidation is received for a block in IS, the block used to be moved to IS_I.
This meant that the data that would arrive in future would be used but not
stored since the controller lost the permissions after gaining them. This
state is being dropped and now invalidation messages would not processed till
the data has arrived. This also means that STALE_DATA type is not longer
required.
Diffstat (limited to 'src/mem/slicc/ast/IfStatementAST.py')
0 files changed, 0 insertions, 0 deletions