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authorBrad Beckmann <Brad.Beckmann@amd.com>2010-08-20 11:46:14 -0700
committerBrad Beckmann <Brad.Beckmann@amd.com>2010-08-20 11:46:14 -0700
commite7f2da517adbc9ba4ed1b33de102126260a0d587 (patch)
treedc45a1acf1843da774f55fb1a5e27333804c4910 /src/mem/slicc/ast/InPortDeclAST.py
parentaf6b97e3ee2d73fcb2d4bcdbdffc9a6534dfdac8 (diff)
downloadgem5-e7f2da517adbc9ba4ed1b33de102126260a0d587.tar.xz
ruby: Stall and wait input messages instead of recycling
This patch allows messages to be stalled in their input buffers and wait until a corresponding address changes state. In order to make this work, all in_ports must be ranked in order of dependence and those in_ports that may unblock an address, must wake up the stalled messages. Alot of this complexity is handled in slicc and the specification files simply annotate the in_ports. --HG-- rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/StallAndWaitStatementAST.py rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/WakeUpDependentsStatementAST.py
Diffstat (limited to 'src/mem/slicc/ast/InPortDeclAST.py')
-rw-r--r--src/mem/slicc/ast/InPortDeclAST.py8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py
index ad48ea4b8..5aa27bae8 100644
--- a/src/mem/slicc/ast/InPortDeclAST.py
+++ b/src/mem/slicc/ast/InPortDeclAST.py
@@ -30,6 +30,8 @@ from slicc.ast.TypeAST import TypeAST
from slicc.symbols import Func, Type, Var
class InPortDeclAST(DeclAST):
+ max_port_rank = 0
+
def __init__(self, slicc, ident, msg_type, var_expr, pairs, statements):
super(InPortDeclAST, self).__init__(slicc, pairs)
@@ -38,6 +40,9 @@ class InPortDeclAST(DeclAST):
self.var_expr = var_expr
self.statements = statements
self.queue_type = TypeAST(slicc, "InPort")
+ if self.pairs.has_key("rank"):
+ InPortDeclAST.max_port_rank = max(self.pairs["rank"],
+ InPortDeclAST.max_port_rank)
def __repr__(self):
return "[InPortDecl: %s]" % self.ident
@@ -126,3 +131,6 @@ class InPortDeclAST(DeclAST):
self.error("InPort declaration not part of a machine.")
machine.addInPort(in_port)
+
+ # Include max_rank to be used by StateMachine.py
+ in_port["max_port_rank"] = InPortDeclAST.max_port_rank