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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-01-29 20:29:17 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-01-29 20:29:17 -0800 |
| commit | c6f1d959be74de55b0c90f3c961314791342d03e (patch) | |
| tree | d0ef0777894828291a6ced188c8bcae323cea442 /src/mem/slicc/ast/MachineAST.py | |
| parent | 98c94cfe3ce83634f3bad79ca18263f42e36ca6a (diff) | |
| download | gem5-c6f1d959be74de55b0c90f3c961314791342d03e.tar.xz | |
ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
Diffstat (limited to 'src/mem/slicc/ast/MachineAST.py')
| -rw-r--r-- | src/mem/slicc/ast/MachineAST.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/slicc/ast/MachineAST.py b/src/mem/slicc/ast/MachineAST.py index ee75b6d6a..0fc79c710 100644 --- a/src/mem/slicc/ast/MachineAST.py +++ b/src/mem/slicc/ast/MachineAST.py @@ -43,6 +43,7 @@ class MachineAST(DeclAST): def files(self, parent=None): s = set(('%s_Controller.cc' % self.ident, '%s_Controller.hh' % self.ident, + '%s_Controller.py' % self.ident, '%s_Profiler.cc' % self.ident, '%s_Profiler.hh' % self.ident, '%s_Transitions.cc' % self.ident, |