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authorBrad Beckmann <Brad.Beckmann@amd.com>2010-08-20 11:46:14 -0700
committerBrad Beckmann <Brad.Beckmann@amd.com>2010-08-20 11:46:14 -0700
commite7f2da517adbc9ba4ed1b33de102126260a0d587 (patch)
treedc45a1acf1843da774f55fb1a5e27333804c4910 /src/mem/slicc/ast/__init__.py
parentaf6b97e3ee2d73fcb2d4bcdbdffc9a6534dfdac8 (diff)
downloadgem5-e7f2da517adbc9ba4ed1b33de102126260a0d587.tar.xz
ruby: Stall and wait input messages instead of recycling
This patch allows messages to be stalled in their input buffers and wait until a corresponding address changes state. In order to make this work, all in_ports must be ranked in order of dependence and those in_ports that may unblock an address, must wake up the stalled messages. Alot of this complexity is handled in slicc and the specification files simply annotate the in_ports. --HG-- rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/StallAndWaitStatementAST.py rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/WakeUpDependentsStatementAST.py
Diffstat (limited to 'src/mem/slicc/ast/__init__.py')
-rw-r--r--src/mem/slicc/ast/__init__.py2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py
index cc5f02b84..b854612be 100644
--- a/src/mem/slicc/ast/__init__.py
+++ b/src/mem/slicc/ast/__init__.py
@@ -57,6 +57,7 @@ from slicc.ast.PairAST import *
from slicc.ast.PairListAST import *
from slicc.ast.PeekStatementAST import *
from slicc.ast.ReturnStatementAST import *
+from slicc.ast.StallAndWaitStatementAST import *
from slicc.ast.StatementAST import *
from slicc.ast.StatementListAST import *
from slicc.ast.StaticCastAST import *
@@ -68,3 +69,4 @@ from slicc.ast.TypeFieldEnumAST import *
from slicc.ast.TypeFieldMemberAST import *
from slicc.ast.TypeFieldMethodAST import *
from slicc.ast.VarExprAST import *
+from slicc.ast.WakeUpDependentsStatementAST import *