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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:51 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:51 -0500 |
| commit | 91a84c5b3cfb888794ac0245c066a4724b9a0871 (patch) | |
| tree | 79a8b41aff56655dbd187934d2709fdd7488c6ed /src/mem/slicc/ast | |
| parent | 9ea5d9cad9381e05004de28ef25309ebe94c3a79 (diff) | |
| download | gem5-91a84c5b3cfb888794ac0245c066a4724b9a0871.tar.xz | |
ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.
Diffstat (limited to 'src/mem/slicc/ast')
| -rw-r--r-- | src/mem/slicc/ast/ActionDeclAST.py | 4 | ||||
| -rw-r--r-- | src/mem/slicc/ast/InPortDeclAST.py | 8 | ||||
| -rw-r--r-- | src/mem/slicc/ast/StallAndWaitStatementAST.py | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/mem/slicc/ast/ActionDeclAST.py b/src/mem/slicc/ast/ActionDeclAST.py index 8015523ab..95a8b6322 100644 --- a/src/mem/slicc/ast/ActionDeclAST.py +++ b/src/mem/slicc/ast/ActionDeclAST.py @@ -48,10 +48,10 @@ class ActionDeclAST(DeclAST): # Add new local vars self.symtab.pushFrame() - addr_type = self.symtab.find("Address", Type) + addr_type = self.symtab.find("Addr", Type) if addr_type is None: - self.error("Type 'Address' not declared.") + self.error("Type 'Addr' not declared.") var = Var(self.symtab, "address", self.location, addr_type, "addr", self.pairs) diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py index da7357580..7a019a0e0 100644 --- a/src/mem/slicc/ast/InPortDeclAST.py +++ b/src/mem/slicc/ast/InPortDeclAST.py @@ -72,9 +72,9 @@ class InPortDeclAST(DeclAST): param_types.append(type) # Check for Address - type = symtab.find("Address", Type) + type = symtab.find("Addr", Type) if type is None: - self.error("in_port decls require 'Address' type to be defined") + self.error("in_port decls require 'Addr' type to be defined") param_types.append(type) @@ -107,9 +107,9 @@ class InPortDeclAST(DeclAST): param_types.append(type) # Check for Address2 - type = symtab.find("Address", Type) + type = symtab.find("Addr", Type) if type is None: - self.error("in_port decls require 'Address' type to be defined") + self.error("in_port decls require 'Addr' type to be defined") param_types.append(type) diff --git a/src/mem/slicc/ast/StallAndWaitStatementAST.py b/src/mem/slicc/ast/StallAndWaitStatementAST.py index 08b0e340c..b2f622871 100644 --- a/src/mem/slicc/ast/StallAndWaitStatementAST.py +++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py @@ -39,7 +39,7 @@ class StallAndWaitStatementAST(StatementAST): def generate(self, code, return_type): self.in_port.assertType("InPort") - self.address.assertType("Address") + self.address.assertType("Addr") in_port_code = self.in_port.var.code address_code = self.address.var.code |