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authorNilay Vaish <nilay@cs.wisc.edu>2013-02-10 21:26:24 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-02-10 21:26:24 -0600
commitd3aebe1f91aa166329c8ee102fdcb2c9734fdceb (patch)
treef6f7807c24eccde98ee1e4bfe4c9c24b3c9392b2 /src/mem/slicc/ast
parentaffd77ea77860fa9231aba8e43ad95dea06a114a (diff)
downloadgem5-d3aebe1f91aa166329c8ee102fdcb2c9734fdceb.tar.xz
ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer class. But to get ruby to compile, the rest of the changes had to be carried out. Subsequent patches will further this process, till we completely replace Time with Cycles.
Diffstat (limited to 'src/mem/slicc/ast')
-rw-r--r--src/mem/slicc/ast/EnqueueStatementAST.py6
-rw-r--r--src/mem/slicc/ast/FuncCallExprAST.py4
-rw-r--r--src/mem/slicc/ast/InfixOperatorExprAST.py43
3 files changed, 29 insertions, 24 deletions
diff --git a/src/mem/slicc/ast/EnqueueStatementAST.py b/src/mem/slicc/ast/EnqueueStatementAST.py
index a8785c9af..329ed30a3 100644
--- a/src/mem/slicc/ast/EnqueueStatementAST.py
+++ b/src/mem/slicc/ast/EnqueueStatementAST.py
@@ -53,8 +53,8 @@ class EnqueueStatementAST(StatementAST):
self.symtab.newSymbol(v)
# Declare message
- code("${{msg_type.ident}} *out_msg = \
- new ${{msg_type.ident}}(curCycle());")
+ code("${{msg_type.ident}} *out_msg = "\
+ "new ${{msg_type.ident}}(curCycle());")
# The other statements
t = self.statements.generate(code, None)
@@ -67,7 +67,7 @@ class EnqueueStatementAST(StatementAST):
try:
# see if this is an integer
latency = int(latency)
- args.append("%s" % latency)
+ args.append("Cycles(%s)" % latency)
except ValueError:
# if not, it should be a member
args.append("m_%s" % latency)
diff --git a/src/mem/slicc/ast/FuncCallExprAST.py b/src/mem/slicc/ast/FuncCallExprAST.py
index b0ab931de..fc42a8a3e 100644
--- a/src/mem/slicc/ast/FuncCallExprAST.py
+++ b/src/mem/slicc/ast/FuncCallExprAST.py
@@ -142,7 +142,7 @@ class FuncCallExprAST(ExprAST):
}
if (result == TransitionResult_ResourceStall) {
- scheduleEvent(1);
+ scheduleEvent(Cycles(1));
// Cannot do anything with this transition, go check next doable transition (mostly likely of next port)
}
@@ -173,7 +173,7 @@ class FuncCallExprAST(ExprAST):
}
if (result1 == TransitionResult_ResourceStall) {
- scheduleEvent(1);
+ scheduleEvent(Cycles(1));
// Cannot do anything with this transition, go check next
// doable transition (mostly likely of next port)
}
diff --git a/src/mem/slicc/ast/InfixOperatorExprAST.py b/src/mem/slicc/ast/InfixOperatorExprAST.py
index c5f384c4b..2f62813df 100644
--- a/src/mem/slicc/ast/InfixOperatorExprAST.py
+++ b/src/mem/slicc/ast/InfixOperatorExprAST.py
@@ -47,7 +47,7 @@ class InfixOperatorExprAST(ExprAST):
rtype = self.right.generate(rcode)
# Figure out what the input and output types should be
- if self.op in ("==", "!="):
+ if self.op in ("==", "!=", ">=", "<=", ">", "<"):
output = "bool"
if (ltype != rtype):
self.error("Type mismatch: left and right operands of " +
@@ -55,30 +55,35 @@ class InfixOperatorExprAST(ExprAST):
"left: '%s', right: '%s'",
self.op, ltype, rtype)
else:
+ expected_types = []
+ output = None
+
if self.op in ("&&", "||"):
# boolean inputs and output
- inputs = "bool"
- output = "bool"
- elif self.op in ("==", "!=", ">=", "<=", ">", "<"):
- # Integer inputs, boolean output
- inputs = "int"
- output = "bool"
+ expected_types = [("bool", "bool", "bool")]
+ elif self.op in ("<<", ">>"):
+ expected_types = [("int", "int", "int"),
+ ("Cycles", "int", "Cycles")]
+ elif self.op in ("+", "-", "*", "/"):
+ expected_types = [("int", "int", "int"),
+ ("Time", "Time", "Time"),
+ ("Cycles", "Cycles", "Cycles"),
+ ("Cycles", "int", "Cycles"),
+ ("int", "Cycles", "Cycles")]
else:
- # integer inputs and output
- inputs = "int"
- output = "int"
+ self.error("No operator matched with {0}!" .format(self.op))
- inputs_type = self.symtab.find(inputs, Type)
+ for expected_type in expected_types:
+ left_input_type = self.symtab.find(expected_type[0], Type)
+ right_input_type = self.symtab.find(expected_type[1], Type)
- if inputs_type != ltype:
- self.left.error("Type mismatch: left operand of operator " +
- "'%s' expects type '%s', actual was '%s'",
- self.op, inputs, ltype)
+ if (left_input_type == ltype) and (right_input_type == rtype):
+ output = expected_type[2]
- if inputs_type != rtype:
- self.right.error("Type mismatch: right operand of operator " +
- "'%s' expects type '%s', actual was '%s'",
- self.op, inputs, rtype)
+ if output == None:
+ self.error("Type mismatch: operands ({0}, {1}) for operator " \
+ "'{2}' failed to match with the expected types" .
+ format(ltype, rtype, self.op))
# All is well
fix = code.nofix()