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authorNilay Vaish <nilay@cs.wisc.edu>2014-09-01 16:55:45 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-09-01 16:55:45 -0500
commitcee8faaad066cda6710904b5190e7287ff9356af (patch)
tree26e2e80ef32a9d82cd6f740d39d15aa229620e5a /src/mem/slicc/ast
parentb1d3873ec52692b0442666718da4175379697bb2 (diff)
downloadgem5-cee8faaad066cda6710904b5190e7287ff9356af.tar.xz
ruby: slicc: change the way configurable members are specified
There are two changes this patch makes to the way configurable members of a state machine are specified in SLICC. The first change is that the data member declarations will need to be separated by a semi-colon instead of a comma. Secondly, the default value to be assigned would now use SLICC's assignment operator i.e. ':='.
Diffstat (limited to 'src/mem/slicc/ast')
-rw-r--r--src/mem/slicc/ast/FormalParamAST.py1
-rw-r--r--src/mem/slicc/ast/ObjDeclAST.py3
-rw-r--r--src/mem/slicc/ast/StallAndWaitStatementAST.py2
3 files changed, 4 insertions, 2 deletions
diff --git a/src/mem/slicc/ast/FormalParamAST.py b/src/mem/slicc/ast/FormalParamAST.py
index 6ed5bca0a..ce73304f1 100644
--- a/src/mem/slicc/ast/FormalParamAST.py
+++ b/src/mem/slicc/ast/FormalParamAST.py
@@ -51,6 +51,7 @@ class FormalParamAST(AST):
v = Var(self.symtab, self.ident, self.location, type, param,
self.pairs)
self.symtab.newSymbol(v)
+
if self.pointer or str(type) == "TBE" or (
"interface" in type and (
type["interface"] == "AbstractCacheEntry" or
diff --git a/src/mem/slicc/ast/ObjDeclAST.py b/src/mem/slicc/ast/ObjDeclAST.py
index ffd71bbb1..92ff15d52 100644
--- a/src/mem/slicc/ast/ObjDeclAST.py
+++ b/src/mem/slicc/ast/ObjDeclAST.py
@@ -29,12 +29,13 @@ from slicc.ast.DeclAST import DeclAST
from slicc.symbols import Var
class ObjDeclAST(DeclAST):
- def __init__(self, slicc, type_ast, ident, pairs, rvalue):
+ def __init__(self, slicc, type_ast, ident, pairs, rvalue, pointer):
super(ObjDeclAST, self).__init__(slicc, pairs)
self.type_ast = type_ast
self.ident = ident
self.rvalue = rvalue
+ self.pointer = pointer
def __repr__(self):
return "[ObjDecl: %r]" % self.ident
diff --git a/src/mem/slicc/ast/StallAndWaitStatementAST.py b/src/mem/slicc/ast/StallAndWaitStatementAST.py
index b87726c6a..08b0e340c 100644
--- a/src/mem/slicc/ast/StallAndWaitStatementAST.py
+++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py
@@ -35,7 +35,7 @@ class StallAndWaitStatementAST(StatementAST):
self.address = address
def __repr__(self):
- return "[StallAndWaitStatementAst: %r]" % self.variable
+ return "[StallAndWaitStatementAst: %r]" % self.in_port
def generate(self, code, return_type):
self.in_port.assertType("InPort")