ruby: Stall and wait input messages instead of recycling

This patch allows messages to be stalled in their input buffers and wait
until a corresponding address changes state.  In order to make this work,
all in_ports must be ranked in order of dependence and those in_ports that
may unblock an address, must wake up the stalled messages.  Alot of this
complexity is handled in slicc and the specification files simply
annotate the in_ports.

--HG--
rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/StallAndWaitStatementAST.py
rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/WakeUpDependentsStatementAST.py

5 files changed, 113 insertions, 0 deletions

diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py
index ad48ea4b8..5aa27bae8 100644
--- a/src/mem/slicc/ast/InPortDeclAST.py
+++ b/src/mem/slicc/ast/InPortDeclAST.py
@@ -30,6 +30,8 @@ from slicc.ast.TypeAST import TypeAST
 from slicc.symbols import Func, Type, Var
 
 class InPortDeclAST(DeclAST):
+    max_port_rank = 0
+    
     def __init__(self, slicc, ident, msg_type, var_expr, pairs, statements):
         super(InPortDeclAST, self).__init__(slicc, pairs)
 
@@ -38,6 +40,9 @@ class InPortDeclAST(DeclAST):
         self.var_expr = var_expr
         self.statements = statements
         self.queue_type = TypeAST(slicc, "InPort")
+        if self.pairs.has_key("rank"):
+            InPortDeclAST.max_port_rank = max(self.pairs["rank"],
+                                              InPortDeclAST.max_port_rank)
 
     def __repr__(self):
         return "[InPortDecl: %s]" % self.ident
@@ -126,3 +131,6 @@ class InPortDeclAST(DeclAST):
             self.error("InPort declaration not part of a machine.")
 
         machine.addInPort(in_port)
+
+        # Include max_rank to be used by StateMachine.py
+        in_port["max_port_rank"] = InPortDeclAST.max_port_rank
diff --git a/src/mem/slicc/ast/PeekStatementAST.py b/src/mem/slicc/ast/PeekStatementAST.py
index 18244f507..cc3091c8a 100644
--- a/src/mem/slicc/ast/PeekStatementAST.py
+++ b/src/mem/slicc/ast/PeekStatementAST.py
@@ -77,6 +77,14 @@ class PeekStatementAST(StatementAST):
     }
             ''')
 
+        if self.pairs.has_key("wake_up"):
+            address_field = self.pairs['wake_up']
+            code('''
+    if (m_waiting_buffers.count(in_msg_ptr->m_$address_field) > 0) {
+        wakeUpBuffers(in_msg_ptr->m_$address_field);
+    }
+            ''')
+
         # The other statements
         self.statements.generate(code, return_type)
         self.symtab.popFrame()
diff --git a/src/mem/slicc/ast/StallAndWaitStatementAST.py b/src/mem/slicc/ast/StallAndWaitStatementAST.py
new file mode 100644
index 000000000..b87726c6a
--- /dev/null
+++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py
@@ -0,0 +1,49 @@
+# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+# Copyright (c) 2009 The Hewlett-Packard Development Company
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class StallAndWaitStatementAST(StatementAST):
+    def __init__(self, slicc, in_port, address):
+        super(StatementAST, self).__init__(slicc)
+        self.in_port = in_port
+        self.address = address
+        
+    def __repr__(self):
+        return "[StallAndWaitStatementAst: %r]" % self.variable
+
+    def generate(self, code, return_type):
+        self.in_port.assertType("InPort")
+        self.address.assertType("Address")
+
+        in_port_code = self.in_port.var.code
+        address_code = self.address.var.code
+        code('''
+        stallBuffer(&($in_port_code), $address_code);
+        $in_port_code.stallMessage($address_code);
+        ''')
diff --git a/src/mem/slicc/ast/WakeUpDependentsStatementAST.py b/src/mem/slicc/ast/WakeUpDependentsStatementAST.py
new file mode 100644
index 000000000..33630a9a4
--- /dev/null
+++ b/src/mem/slicc/ast/WakeUpDependentsStatementAST.py
@@ -0,0 +1,46 @@
+# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+# Copyright (c) 2009 The Hewlett-Packard Development Company
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class WakeUpDependentsStatementAST(StatementAST):
+    def __init__(self, slicc, address):
+        super(StatementAST, self).__init__(slicc)
+        self.address = address
+        
+    def __repr__(self):
+        return "[WakeUpDependentsStatementAst: %r]" % self.variable
+
+    def generate(self, code, return_type):
+        self.address.assertType("Address")
+        address_code = self.address.var.code
+        code('''
+        if (m_waiting_buffers.count($address_code) > 0) {
+            wakeUpBuffers($address_code);
+        }
+        ''')
diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py
index cc5f02b84..b854612be 100644
--- a/src/mem/slicc/ast/__init__.py
+++ b/src/mem/slicc/ast/__init__.py
@@ -57,6 +57,7 @@ from slicc.ast.PairAST import *
 from slicc.ast.PairListAST import *
 from slicc.ast.PeekStatementAST import *
 from slicc.ast.ReturnStatementAST import *
+from slicc.ast.StallAndWaitStatementAST import *
 from slicc.ast.StatementAST import *
 from slicc.ast.StatementListAST import *
 from slicc.ast.StaticCastAST import *
@@ -68,3 +69,4 @@ from slicc.ast.TypeFieldEnumAST import *
 from slicc.ast.TypeFieldMemberAST import *
 from slicc.ast.TypeFieldMethodAST import *
 from slicc.ast.VarExprAST import *
+from slicc.ast.WakeUpDependentsStatementAST import *