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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:13 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:13 -0500 |
| commit | b7153e2a64bdb88cebe96e59b24d5597a3a42205 (patch) | |
| tree | 85457e768fc4f42e978e005e2a04f58baaf84654 /src/mem/slicc/generate/html.py | |
| parent | af0f8b31dbbc105c1a07d94265824cee4bda0c55 (diff) | |
| download | gem5-b7153e2a64bdb88cebe96e59b24d5597a3a42205.tar.xz | |
mem: Separate out the different cases for DRAM bus busy time
This patch changes how the data bus busy time is calculated such that
it is delayed to the actual scheduling time of the request as opposed
to being done as soon as possible.
This patch changes a bunch of statistics, and the stats update is
bundled together with the introruction of tFAW/tTAW and the named DRAM
configurations like DDR3 and LPDDR2.
Diffstat (limited to 'src/mem/slicc/generate/html.py')
0 files changed, 0 insertions, 0 deletions