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authorPouya Fotouhi <pfotouhi@ucdavis.edu>2019-02-27 13:25:22 -0800
committerPouya Fotouhi <pfotouhi@ucdavis.edu>2019-07-23 16:59:39 +0000
commit6f45523ed7305f290e0cc1cc475df13c8ab22b3e (patch)
treee9fba72ad3e991d1fb1a6d8f177a60ec57d58f60 /src/mem/slicc/main.py
parent2757368c842e445b7dad79941172e396a14d58d5 (diff)
downloadgem5-6f45523ed7305f290e0cc1cc475df13c8ab22b3e.tar.xz
mem-ruby: Adding a new slicc statement - to not evict locked cachelines
Ruby caches block incoming ports with messages on a locked address to make sure the line would not be replaced by others. But they do not check the lock upon capacity/conflict misses. This change adds a new slicc statement "check_on_cache_probe" which takes two arguments (mandatoryQueue for the controller, and the line subject to eviction - i.e. address returned by cacheProbe). If the line is locked, incoming message is delayed for 1 cycle and the controller skips this request (i.e. does not trigger an event). Coherence protocols should be updated accordingly. One use case for MESI Two Level will be added in a separate change. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: I79ca2d45518de7a4e382b520a11f8e221b0cb803 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16808 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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