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| author | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 17:11:36 -0600 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 17:11:36 -0600 |
| commit | 07ea0891f1699f6194a05516948ce3824fb8fb38 (patch) | |
| tree | b5c22e3fe49a7e0d277fdb9ac5ee87c2aa0321e5 /src/mem/slicc/parser.py | |
| parent | 279f179babc9e5663156777c533c06edc91bce9a (diff) | |
| download | gem5-07ea0891f1699f6194a05516948ce3824fb8fb38.tar.xz | |
ruby: new atomics implementation
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
Diffstat (limited to 'src/mem/slicc/parser.py')
| -rw-r--r-- | src/mem/slicc/parser.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py index 6c3f45629..226106678 100644 --- a/src/mem/slicc/parser.py +++ b/src/mem/slicc/parser.py @@ -514,8 +514,8 @@ class SLICC(Grammar): p[0] = ast.EnqueueStatementAST(self, p[3], p[5], p[6], p[8]) def p_statement__peek(self, p): - "statement : PEEK '(' var ',' type ')' statements" - p[0] = ast.PeekStatementAST(self, p[3], p[5], p[7], "peek") + "statement : PEEK '(' var ',' type pairs ')' statements" + p[0] = ast.PeekStatementAST(self, p[3], p[5], p[6], p[8], "peek") def p_statement__copy_head(self, p): "statement : COPY_HEAD '(' var ',' var pairs ')' SEMI" |